Printed Resistors in RC Timing Circuits: Separate Threshold Drift from Resistance Drift

System boundary

The guide covers a printed resistor's role in a first-order threshold-crossing delay. It does not assign timer-IC accuracy, oscillator stability, certified safety timing or a capacitor technology's operating properties.

Integration interfaces

Integration risks

Define where the timing interval starts and ends

Distinguish trigger arrival, release of a reset switch, start of capacitor charging and the final output transition. Those events can be separated by propagation or recovery delays. A measured output pulse width is not automatically identical to the capacitor's charging interval. Record which two events define the customer's timing requirement.

Identify the printed resistor, external capacitor, charge source, threshold detector and discharge path. A timer IC can implement several of these functions, but its actual operating mode and device limits remain relevant. A generic one-shot formula does not establish a permitted trigger pulse or a complete startup sequence for every circuit.

Separate the time constant from the threshold factor

For a constant source Vs charging a capacitor through R from initial voltage V0, the capacitor approaches Vs exponentially. Solving for the time at which it reaches VH gives RC multiplied by a logarithm. That factor changes when the threshold or starting state changes, even if the RC product stays constant.

The expression requires Vs greater than VH and VH greater than V0 for the charging transition considered here. A threshold above the attainable asymptote is not a very long valid delay; it is an unreachable crossing in this model. Discharge timing uses its own initial and final boundaries rather than copying the charging equation blindly.

Compare threshold movement with resistor movement

Assume R = 100 kΩ, C = 100 nF and V0 = 0, giving RC = 10 ms. With VH equal to two thirds of Vs, the charging time is 10 ln(3), approximately 10.986 ms. Increasing R by 1% increases that ideal interval by exactly 1% when every other input is fixed.

Keep R and C unchanged but move the threshold fraction to 0.68 of Vs. The time becomes −10 ln(0.32), approximately 11.394 ms, about 3.72% longer. This illustrative threshold change is not a timer tolerance specification. It demonstrates why a timing error larger than the measured resistor change can originate elsewhere in the circuit.

Check the capacitor state left by reset

A reset switch has finite resistance and limited available reset time. The capacitor may not return to the assumed starting voltage before the next trigger. With the same example and an initial voltage of 0.05 Vs, the interval becomes 10 ln(0.95/(1/3)), approximately 10.473 ms. The shorter delay is caused by the starting state, not by a lower printed resistance.

Compare the first event after a long idle interval with repeated events at the required cadence. Preserve the actual capacitor voltage immediately before charging. Dielectric absorption, charge injection and a disturbed reset path can also affect that state. Do not trim the resistor to correct one repetition rate while leaving the reset mechanism unexplained.

Include leakage in the attainable charging voltage

A current drawn from the timing node reduces the current available to charge the capacitor. In a simplified constant-leakage model, the asymptotic voltage becomes Vs minus R times the leakage current, while the time constant remains RC. Use that changed asymptote in the crossing calculation, provided the constant-current assumption is reasonable.

Increasing resistance to obtain a longer delay makes a given leakage current more influential. Input bias, capacitor leakage, surface contamination and connected test instruments can contribute through different dependencies. A large timing capacitor or a lower resistance has its own loading and reset trade-offs. Select the complete circuit rather than treating resistance scale as a free adjustment.

Use capacitor and threshold records to locate the error

Measure the capacitor waveform with a suitably low-loading method and retain the trigger, reset and output events on the same time base. The following distinctions help avoid changing a correct resistor to compensate for a different error.

Evaluate supply and temperature on the correct circuit basis

If both the source and threshold scale ideally with the same supply, the normalized logarithmic factor can remain constant. A fixed independent threshold does not share that cancellation. Real detector offset, output saturation and reset behavior can also prevent ideal scaling. Record actual node voltages instead of asserting that every RC timer is supply independent.

Temperature can change resistor value, capacitance, leakage and detector thresholds through different mechanisms. A resistor TCR allocation addresses only one branch. Keep the component and circuit measurements tied to the same state, and preserve correlated changes where they exist. A room-temperature trim cannot automatically remove a temperature-dependent threshold error.

Specify resistance from the complete timing allocation

The network request should state nominal resistance, its allowed contribution to the timing error, capacitor conditions, threshold bounds, reset state and event cadence. Include the permissible adjustment direction if laser trimming is proposed. Adjusting a resistor changes charging current and may change the relative importance of leakage or detector loading.

Validate the complete circuit across its required supply, temperature, trigger and output-load states. Keep measured delay, individual component values and waveform evidence separate in the report. ChipSimple's printed resistor review does not certify a timer, oscillator or safety delay; the application owner must verify the final event behavior and any protective function.