Ceramic and metallization route
Confirm alumina or AlN grade, thickness, surface condition, conductor system, gold route and thickness, adhesion, firing or finishing compatibility, and assembly use.

Two-sided ceramic metallization
Double-sided gold-plated ceramic PCBs place drawing-defined metallization and assembly features on both faces of a ceramic substrate. Chipsimple reviews ceramic grade, thickness, front-to-back artwork, hole and edge features, conductor or finish route, registration, bonding or soldering interface, continuity, isolation, and inspection before release.
These ceramic thick film values support early material and geometry selection. Ceramic grade, two-sided artwork, conductor system, finish thickness, holes, edge features, registration, any through-connection route, assembly interface, continuity, isolation, and inspection are released from the controlled drawing.
Final values confirmed against customer drawing.
| Substrate Material | 96% / 99% / 99.6% Alumina / AlN |
|---|---|
| Board Thickness | 0.25–3.0 mm |
| Conductor System | Ag / Ag-Pd / Pt-Ag / Au |
| Resistor System | RuO₂ thick film |
| Conductor Thickness | 10–25 µm typical |
| Resistance Tolerance | ±1% standard (±0.5% available) |
| Firing Temperature | Up to 850°C |
|---|---|
| Thermal Conductivity | ≥24 W/m·K, 96% alumina reference |
| Minimum Line/Space | ≥100 µm |
| Board Size | Max. 120 × 120 mm; larger on request |
| Surface Finish | Bare Ag / ENIG / ENEPIG |
| Dielectric Strength | ≥15 kV/mm |
A two-sided ceramic PCB is reviewed face by face and interface by interface. Engineering connects substrate properties, front and back artwork, fiducials, hole preparation, edge geometry, compatible conductor and finish, refire sequence, masking, bonding or soldering surfaces, interconnect definition, dimensional tolerance, continuity, isolation, and handling risk.
Confirm alumina or AlN grade, thickness, surface condition, conductor system, gold route and thickness, adhesion, firing or finishing compatibility, and assembly use.
Release both face artworks with fiducials, datums, holes, edge contacts, scallops, mask areas, alignment tolerances, and a clear layer sequence.
Define whether holes are mechanical, metallized, filled, or electrically connected, plus bonding, soldering, contact, mounting, cleaning, and downstream thermal conditions.
Specify dimensions, appearance, finish thickness if required, adhesion, front-to-back continuity, isolation, contact or bondability, sampling, and acceptance limits.
Two-sided gold-interface ceramic boards can support compact modules when the interconnect, assembly process, thermal path, and electrical inspection are explicitly released.
Application illustrationCompact power-control assemblies require reviewed thermal path, isolation, conductor current, die or component attach, wire bonding or soldering, and inspection conditions.
Review application inputs
Application illustrationGold-interface ceramics can be considered only after line geometry, finish, grounding, loss, attachment, cleanliness, frequency, and RF validation requirements are defined.
Review application inputs
Application illustrationAvionics and industrial hybrids require program-specific material declarations, traceability, bonding, thermal cycling, vibration, electrical tests, and qualification evidence.
Review application inputsThe verified photographs show white ceramic parts with gold-colored surface metallization, holes, scalloped edges, repeated pad and rail patterns, and at least two visible face designs. Surface views cannot prove substrate grade, gold thickness, hidden layers, plated-through holes, front-to-back electrical continuity, adhesion, or bondability.

Chipsimple supports controlled printing, thermal processing, laboratory inspection, and managed production in Dongguan. Two-sided ceramic projects release the substrate, both artworks, conductor and finish route, interconnect definition, assembly surfaces, electrical tests, sampling, traceability, and acceptance records together; special bonding claims require project validation.
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Short answers for quotation planning; released drawings and validation requirements remain controlling.
Define ceramic grade and thickness, both face artworks, datums, holes and edge features, conductor and gold route, required finish thickness, front-to-back interconnect, bonding or soldering method, current, voltage, isolation, thermal conditions, dimensions, cleanliness, inspection, and downstream assembly profile.
No. They are practical category-level selection values, not a released product specification. Material compatibility, geometry, print build, electrical loading, assembly, environment, inspection method, and expected volume can narrow the usable window. Final values are confirmed against the controlled drawing and approved project conditions.
Verify dimensions, flatness and visual criteria, front-to-back registration, conductor and finish condition, adhesion, required thickness, continuity and isolation, plus solderability, contact, or wire-bond tests that match the intended assembly. Hole metallization and electrical continuity must be tested, not inferred from appearance.
Send the controlled drawing or artwork, dimensions and tolerances, material preference, electrical targets, assembly interface, operating environment, validation requirements, prototype quantity, annual volume, and schedule. Include separate front and back data, the hole/interconnect definition, gold process and thickness, assembly method, and continuity or isolation limits.
Send separate front and back artwork with the ceramic, hole, interconnect, finish, assembly, and electrical requirements. Clear definitions for metallized holes, gold thickness, bonding or soldering, continuity, isolation, and datums prevent surface appearance from being mistaken for a released two-sided connection.
PDF, DWG, DXF, STEP, Gerber, ZIP, Excel, Word, or sample photos are accepted.
