Ceramic Sensor Acquisition: Check the SAR Reference During Bit Decisions

System boundary

A ceramic resistor or resistive sensor network, its signal conditioning, a SAR ADC, reference driver and local reference connections. The actual converter architecture controls charge demand and timing; the simplified example is not a model of every SAR device.

Integration interfaces

Integration risks

Draw signal and reference paths separately

Identify the ADC signal input, reference input and their corresponding returns on the actual circuit. The signal path may include a printed divider, gain network and buffer. The reference path can use a different source and local capacitor. Calling both nodes analog voltage hides their different loading and timing requirements. Preserve each path through connectors, shared returns and any active stages.

The reference is not simply a high-impedance DC measurement input. In a traditional SAR architecture, internal switching associated with conversion places dynamic demands on it. The selected converter documentation determines those demands. A resistor ratio measured correctly at the signal input does not verify the reference source or its local connections.

Consider the reference at each successive decision

A simplified unipolar two-bit SAR conversion first compares the input with one half of the reference. After retaining or clearing that trial bit, it tests the next bit using a different internal DAC level. With a constant reference, these trials produce the familiar four code intervals. With a changing reference, the thresholds encountered during one conversion need not be scaled by the same factor.

This distinction matters when interpreting a calibration error. A constant reference offset can behave like a scale error over an ideal range. A disturbance that occurs only during selected decisions can move particular transitions differently. One endpoint gain correction cannot generally repair that pattern. Real converters use architecture-specific switching, so the example establishes the question rather than predicting their exact codes.

Use a small code example to expose the timing error

Assume an ideal two-bit unipolar converter with a 5.00 volt reference and an input of 3.70 volts. The first threshold is 2.50 volts, so the upper bit is retained. The second trial threshold is 3.75 volts, so the lower bit is cleared. The resulting code is binary ten, or decimal two. The example uses conventional ideal thresholds and excludes offset and noise.

Now keep the first reference decision at 5.00 volts but assume the reference is 4.90 volts during the second trial. Its three-quarter threshold becomes 3.675 volts. The same 3.70 volt input now retains the lower bit and produces decimal three. This deliberately exaggerated disturbance makes the mechanism visible. It is not a permissible reference variation or a measured converter defect.

Check local charge delivery without prescribing a capacitor

For an ideal isolated capacitor, extraction of charge delta Q causes a voltage change delta Q divided by capacitance. This is a useful scale check for a short demand supplied locally. It does not include simultaneous buffer replenishment, capacitor impedance or the converter's detailed switching. Those contributions are essential when designing the real reference circuit.

For assumed charge extraction of 2 nanocoulombs from an effective 10 microfarad capacitor, the ideal change is 0.20 millivolt. Relative to 5 volts that is 40 parts per million. At an ideal sixteen-bit full-scale boundary, a half-code reference allocation is approximately 38.15 microvolts. The comparison shows why a small-looking transient may matter, but does not establish that every decision experiences the full calculated step.

Keep the reference return inside the observed boundary

Measure the voltage relevant to the converter: reference pin relative to its designated local return. A stable source output measured against a remote ground can coexist with movement at that boundary. Short current pulses encounter connection inductance and shared impedance; a nearby capacitor can be ineffective if its return makes a large loop. Record physical placement, not only the schematic value.

Use probing that does not materially change the path being investigated. Added capacitance, lead inductance or an unsuitable probe reference can create or suppress an apparent disturbance. The electrical validation owner should establish the required bandwidth, loading and uncertainty. Do not conclude that the reference is quiet merely because a long-lead oscilloscope capture lacks a visible pulse.

Vary input code and conversion activity independently

Keep the analog input source stable and examine a set of relevant input levels while retaining conversion-synchronous reference observations. Different internal switching histories can load the reference differently. Include transition regions that matter to the application rather than measuring only zero and full scale. Preserve raw output codes without smoothing away an abnormal transition.

Then compare permitted conversion rates and activity patterns while leaving the input circuit unchanged. A reference source that appears adequate during sparse conversions may behave differently under continuous demand. This test is separate from the divider-input reservoir calculation: verify that the input has already settled and observe the reference path directly so changes are not assigned to the wrong analog node.

Review the buffer and capacitor as a coupled choice

A reference source's static accuracy does not specify its response to the converter's fast load. Check the supported load, dynamic output impedance, stability with the proposed capacitor and the applicable conversion conditions. Use device-specific guidance rather than transferring a capacitor value from an unrelated reference design. Capacitance under actual bias and temperature may differ from its nominal marking.

If the reference comes from a resistor network, distinguish the accurate DC ratio from the drive function. A buffer can isolate that network from dynamic load but introduces its own errors and operating limits. Keep reference noise and long-term drift in their existing budget; neither explains away an unverified bit-decision transient. The complete path must satisfy both static and dynamic requirements.

Keep passive scaling and converter behaviour independently traceable

The final record should include the signal-network measurements, reference source and capacitor identities, board or ceramic interconnect layout, conversion timing and observed transition behaviour. Retain the raw reference waveforms and code data with the same configuration identifier. A later converter or buffer substitution can alter the dynamic load even when the nominal reference voltage remains unchanged.

ChipSimple can review the drawing-defined resistor network and its passive accuracy allocation. The customer's acquisition team verifies the active reference drive and completed conversion channel. Maintaining those separate results prevents a converter timing problem from becoming an unnecessary resistor trim change, and makes a genuine passive-network change visible without reinterpreting every code error as a material defect.