Matched RC Input Filters: Preserve Common-Mode Rejection

System boundary

Two low-pass RC input legs feeding a differential amplifier from a defined source, including their resistor network, capacitors, source impedances and reference return. A capacitor directly between the inputs requires an extended model.

Integration interfaces

Integration risks

Name the two filter legs before calculating rejection

Consider a source that applies the same small AC voltage to two inputs. Each input passes through a series resistance and then a capacitor to the same low-impedance AC reference. An ideal high-impedance differential receiver observes the two filtered nodes. Label their time constants tau1=R1C1 and tau2=R2C2, including source resistance when it belongs in series with the printed element.

This intentionally simple topology exposes the mismatch mechanism. A real instrument may include a capacitor directly across the amplifier inputs, protection devices or a source with unequal impedance. Preserve those components in the actual circuit model rather than treating the following independent-leg result as universal. The passive ceramic network and the complete active channel are different acceptance boundaries.

Subtract the complex responses, not their magnitudes

For the independent first-order legs, H1=1/(1+j omega tau1) and H2=1/(1+j omega tau2). Their differential output from a common input is proportional to H1−H2. Magnitude and phase both matter. Subtracting the two gain magnitudes alone misses conversion caused by phase mismatch and can predict zero error when the complex voltages are unequal.

The exact magnitude of that conversion is omega times the absolute time-constant difference divided by the product of the two first-order denominator magnitudes. It vanishes at DC in this ideal capacitive model, grows around the filter transition and eventually falls again. DC bias-current offset and DC gain-ratio mismatch are separate effects with different equations and tests.

Translate a small time-constant difference into an input error

Take assumed time constants of 10.0 and 10.1 microseconds. At omega=100000 radians per second, or about 15.915 kilohertz, the two normalized frequencies are 1 and 1.01. The conversion magnitude is approximately 0.004975. A common-mode disturbance of 1 volt peak therefore produces about 4.975 millivolts peak of unwanted differential input in this simplified circuit.

If the following receiver has differential gain twenty and remains linear over this band, that input term alone produces roughly 99.5 millivolts peak at its output. These assumed values illustrate a design calculation, not a measured network result or a promised amplifier bandwidth. They show why a one-percent time-constant difference can matter when the wanted signal is much smaller than the common-mode disturbance.

Allocate resistor and capacitor mismatch together

For small variations, a leg's fractional time-constant change is approximately its fractional resistance change plus its fractional capacitance change. The difference between the two legs therefore contains both pair mismatches. A tightly matched resistor pair cannot cancel an unknown capacitor mismatch reliably across temperature, applied voltage and aging. Accidental cancellation at one measured state is not a stable design assumption.

Include cable capacitance, input capacitance and source resistance where they materially affect the time constants. A symmetric drawing can become electrically asymmetric when one input receives a longer wire or an extra protection part. Specify which contributions are controlled by the thick-film network and which belong to the assembled channel. Use measured pairs or justified limits rather than assigning every component the same generic percentage.

Recompute the network when a differential capacitor is added

A capacitor placed directly between the two filtered inputs provides a path for differential voltage. Under a perfectly symmetric common-mode excitation it carries no differential current, but when the legs mismatch it participates in the response. It can reduce conversion in suitable designs while changing the wanted differential bandwidth. It does not simply make all capacitors interchangeable.

Solve the two coupled node equations with the actual capacitor values, resistor values and amplifier input model. Verify the wanted differential response as well as common-mode rejection after the change. A filter that removes an unwanted disturbance but excessively attenuates or delays the sensor signal is not an acceptable improvement merely because one rejection measurement looks better.

Separate passive conversion from other channel errors

Use deliberate input modes to identify what the channel is doing. Keep the same source and receiver references while changing the excitation type. The purpose is to distinguish mechanisms that can look like one output error but require different hardware decisions.

Verify the stimulus before blaming the resistor network

Connect the common-mode test source so both input boundaries receive the intended equal waveform. Unequal cable paths, generator impedances or probe loading can create an artificial differential signal. Characterize that imbalance before interpreting the amplifier output as the filter's rejection. Use appropriate signal levels to keep every input, reference and output inside its operating region.

Record phase and amplitude over the required band rather than one mains-frequency point. Repeat a limited comparison with intentionally changed known time constants to test whether the observed trend follows the model. Keep noise floors and measurement uncertainty with the result. An apparent rejection floor may belong to the stimulus or analyzer, not to the printed resistor pair.

Use one amplitude convention throughout the error budget. A peak disturbance multiplied by a transfer magnitude yields a peak error; an RMS limit requires the corresponding waveform conversion. Do not compare those numbers directly simply because both carry volt units.

Keep passive matching and assembled rejection as linked requirements

The resistor-network drawing should identify both input elements, absolute resistance range, matching requirement and temperature conditions. The circuit handoff should add the capacitors, source impedance, common-mode spectrum, differential signal range and permitted error. A network resistance test verifies its assigned contribution; an assembled injection sweep verifies the complete filtering and receiver chain.

Retain the frequency-response data with component identities and wiring configuration. Reopen the review after changing capacitor technology, input protection, cable routing, sensor source impedance or amplifier. Do not compensate a frequency-dependent conversion by adjusting a static output offset. The useful release decision is an error budget and test envelope that remain meaningful after the ceramic network becomes part of the customer's instrument.