R-2R Thick Film Resistor Networks: Review Bit Weight and Output Loading

System boundary

The guide covers a passive voltage-mode R-2R network and its connected static bit weights. Current-output DACs, output amplifiers, switching transients and final conversion accuracy require their own circuit definitions and validation.

Integration interfaces

Integration risks

Define the ladder and its termination

Consider a two-bit voltage-mode example. Output node A connects through 2R to the most-significant bit voltage V1 and through R to node B. Node B connects through 2R to the least-significant bit voltage V0 and through another 2R to ground. Each bit voltage is ideally either zero or the same reference Vref.

The terminating 2R resistor is part of the circuit, not an optional end detail. This topology differs from a current-output multiplying DAC with an amplifier maintaining a virtual ground. Keep the actual terminal map and mode in the network drawing. A generic R-2R label cannot establish which transfer equation or output impedance applies.

Derive the two bit weights from node equations

With no output load and ideal bit-voltage sources, current balance at node B gives 4VB − 2VA − V0 = 0. At node A it gives 3VA − 2VB − V1 = 0. Solving the pair produces VA = V1/2 + V0/4. The two weights arise from the complete connected ladder, including its termination.

This derivation also provides a useful netlist check. Reversing bit labels, omitting the terminating resistor or taking the output from a different node changes the result. Verify connections before blaming a resistor process. A continuity map and nominal resistance list should describe the same ladder used in the calculation.

Check the code table before adding error terms

With an assumed 4 V reference, the ideal codes produce 0, 1, 2 and 3 V. The highest code is three quarters of the reference, not the reference itself. In this example, the ideal step is 1 V. These values illustrate binary weighting and are not a proposed commercial DAC resolution or output specification.

Separate a constant loading gain from bit-weight error

With all ideal bit sources set to zero for a Thevenin resistance calculation, the stated ladder presents output resistance R. A load RL therefore multiplies the unloaded voltage by RL/(R + RL). For R = 10 kΩ and RL = 90 kΩ, that factor is 0.9, as shown in the table.

In this ideal case the load creates a common gain reduction, not unequal code spacing. A real switch network or nonlinear load can make the effective impedance state dependent and requires a fuller calculation. A buffer reduces loading only if its input range, bias current, output swing and stability meet the connected requirements. It does not automatically correct the ladder's internal ratios.

Treat switch resistance as part of a rung

Suppose the most-significant 20 kΩ rung in the R = 10 kΩ example acquires an additional assumed 100 Ω in series. Keeping the other branches ideal, code 10 produces approximately 1.9950 V and code 01 approximately 1.0025 V. The major carry from 01 to 10 is then about 0.9925 V rather than 1 V.

This fixed extra resistance illustrates unequal bit weights. Real switch resistance can vary with signal, supply and state, so the added impedance may not even be constant. Use the selected switching circuit's data and operating conditions; do not assign a universal acceptable switch resistance from a nominal R value. Reference-source drops and ground-return drops belong in the same connected-circuit review.

Specify matching independently from absolute scale

Scaling every ideal ladder resistor by the same factor leaves the unloaded DC bit weights unchanged but changes output resistance and loading. Differential changes between rungs or between R and 2R alter weights. A network specification should therefore distinguish common scale, internal relationships and external parasitic contributions.

For a larger ladder, the important relationships depend on position and topology. Do not assign a converter bit count from a printed resistor tolerance without a complete error analysis. Thermal gradients can also make different branches operate at different temperatures. A shared substrate does not prove identical self-heating or perfect ratio tracking under every digital pattern.

Measure bit contributions and carry transitions separately

Record individual bit-on outputs, zero code, full-scale code and relevant adjacent transitions with the actual reference, switches and load. A full-scale gain adjustment can hide unequal individual weights. The carry transition is particularly informative because one more-significant contribution replaces several less-significant contributions.

Keep settled DC results separate from transient behavior. Several switches may change at different instants during a carry, producing a glitch even if the final values are correct. Output capacitance and the receiver can affect settling. Define when the output is considered valid and retain the actual transition waveform where dynamic performance matters; resistor matching alone cannot establish it.

Hand off a circuit-linked resistor requirement

The drawing package should contain the full ladder, bit significance, termination, reference and ground boundaries, output load and switching model. Specify the error allocation assigned to the passive network separately from active devices and reference behavior. Include accessible measurement nodes and the code set used for verification.

If trimming is proposed, identify which resistors may change and the permitted direction. Verify the complete code relationships after adjustment rather than optimizing a single convenient output. ChipSimple can review a drawing-defined thick-film network; that does not imply a catalogue DAC product, guaranteed converter resolution or complete system performance.