Zero-Crossing Detectors: Separate Resistor-Threshold Bias from Comparator Delay

System boundary

A resistor-defined analog threshold, comparator and edge-capture input under a specified signal envelope; excludes complete mains safety or oscillator design.

Integration interfaces

Integration risks

Define which crossing the receiving system needs

A zero crossing can mean the instant a ground-referenced waveform crosses zero, or the instant an AC component crosses a defined baseline. If that baseline moves, identify how it is estimated and its permitted tracking error. A fixed reference and a dynamic baseline circuit do not create the same threshold history. State the intended rising or falling event and the input location at which it is defined.

The digital receiver observes another event: for example, a comparator output crossing a logic threshold or a timer capturing an edge. Include that threshold and the capture path in the timing boundary. The resistor network contributes to the analog threshold, but does not determine comparator internal delay or a controller's synchronization latency. Keep these owners separate in the specification.

Establish the actual threshold before converting it to time

Define the effective switching threshold relative to the intended analog baseline. It can include the resistor-defined reference, comparator input offset, input-current drop through source impedance and the applicable hysteresis state. Use the already established loaded-threshold calculation rather than assuming a resistor ratio directly equals the complete switching voltage.

Hysteresis can create different effective thresholds for rising and falling input. Record both. A detector can suppress chatter while deliberately moving its edge away from the ideal zero crossing. More hysteresis is therefore not a free improvement in timing precision. It must fit both the noise-handling need and the permitted phase or timestamp error.

Convert a small threshold error through the crossing slope

Near a monotonic crossing, a small threshold displacement produces an approximate time displacement equal to voltage displacement divided by the waveform slope. The slope is signed. A positive threshold shift delays a rising crossing but can advance the corresponding falling crossing relative to the waveform's zero. Define the sign of the reported timing error as observed threshold crossing minus ideal crossing.

This local calculation is useful only when the slope is resolved and sufficiently constant over the displacement. Near a flat peak, a small voltage change can cause a large timing change or eliminate the crossing. Do not divide by an arbitrary small slope to force a precise answer. Check that the waveform reaches the relevant threshold under the minimum-amplitude condition.

Use an exact sine crossing to check the approximation

For an illustrative rising sine v(t)=A sin(2πft) with ideal zero crossing at t=0, the actual threshold crossing is asin(VT/A)/(2πf) when the selected nearby branch exists and the magnitude of VT is less than A. Let A be 1 V, f be 50 Hz and VT be plus 20 mV. The threshold crossing occurs approximately 63.666 microseconds late.

If the comparator's additional delay under that exact operating condition is assumed to be 10 microseconds, its observed edge is about 73.666 microseconds late before other capture contributions. Reducing amplitude to 0.5 V with the same threshold gives about 127.358 microseconds of threshold delay. A fixed time correction learned at 1 V therefore does not remove the error at the lower amplitude. These are hypothetical values, not device or manufacturing specifications.

Do not substitute a headline propagation number for the operating condition

Comparator response depends on the input condition as well as the device. Data sheets commonly state propagation delay at a particular input overdrive and loading. Read the test definition and the relevant variation data. A fast step test at large overdrive is not automatically representative of a slowly changing small signal near the switching point.

Keep low-to-high and high-to-low output delays separate. Output loading, an open-drain pull-up and the receiver's logic threshold can alter the observed edge. A delay measured to the midpoint of the comparator output is not necessarily the delay to the controller's capture threshold. Characterize the complete installed boundary rather than adding the full output rise time to a propagation specification that already includes part of that transition.

Separate a repeatable timing offset from edge-to-edge variation

A constant threshold error creates a systematic shift for a fixed waveform. Noise near the crossing creates timing variation whose small-signal scale depends on local slope. Under a justified small-noise model, an input voltage standard deviation divided by the magnitude of the crossing slope provides a first timing-jitter estimate. Correlated noise, repeated crossings and comparator behavior can invalidate that simple estimate.

Record individual edge errors rather than only an averaged waveform. Averaging can make a jittering edge appear smooth while hiding the distribution relevant to the receiver. Also compare amplitude and frequency states. A threshold contribution changes with waveform slope, whereas a fixed capture latency behaves differently. Neither pattern alone proves a component fault, but the controlled comparison helps identify the next measurement.

Observe the analog threshold and digital event on a common time base

Use instrumentation and probing suitable for the voltage, bandwidth and source impedance. Record the input waveform near the crossing, the reference or threshold state where accessible, and the digital output under its intended load. Account for channel timing skew before interpreting small differences. A probe that changes the threshold network can alter the event being measured.

Compare the observed input crossing with the output event to estimate the active and output-path contribution separately from threshold displacement. Repeat relevant amplitudes, frequencies, supply states and both directions. For hazardous or mains-related signals, the system owner must provide the required isolation and safe measurement arrangement; a printed resistor network or this low-voltage example does not establish a safe direct connection.

Specify voltage and timing allocations together

Provide the intended crossing, minimum signal amplitude and slope, baseline behavior, hysteresis and permitted timestamp error. Assign the threshold network an allowable voltage contribution derived from the worst relevant slope, not from an arbitrary resistance tolerance. Preserve a separate budget for active-device delay, signal conditioning and digital capture.

For a custom printed resistor network, include the loaded schematic, individual and ratio requirements, reference source and receiver boundary. Validate the assembled detector after any trim or component substitution. The useful output is a timing budget and measurement that remain valid across the defined signal envelope, rather than a single calibrated edge that happens to agree at one operating point.