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Two resistor networks can present exactly the same DC behavior at all three external terminals and still dissipate their heat in different printed elements. Passing the terminal electrical check therefore does not transfer an internal voltage or thermal assessment to the replacement. A substitution review needs both the equivalent external circuit and the real element-level stress map.
System boundary
A passive three-terminal printed resistor network whose topology may change between star and delta while preserving DC terminal behavior. The examples are asymmetric low-voltage networks, not balanced three-phase heater reconnection, installation guidance or approval of a particular material.
Integration interfaces
| Interface | Required input | Thick film role | Validation owner |
|---|---|---|---|
| External analog circuit to network terminals | Terminal voltages or connected source/load models for each operating state. | Present the drawing-defined passive terminal relation. | Analog circuit designer. |
| Equivalent schematic to individual printed elements | Physical element resistance, geometry and solved voltage/current. | Dissipate local electrical power in the actual printed pattern. | Network layout and thermal reviewers. |
| Internal junction to test or protection connection | Whether the star center is truly internal and electrically unloaded. | Preserve the stated number of accessible circuit nodes. | System schematic owner. |
Integration risks
| Risk | Control or verification | Validation owner |
|---|---|---|
| Equal terminal behavior is accepted as equal internal element stress. | Compare a per-element power and voltage table for both physical topologies. | Substitution reviewer. |
| A star-center connection is omitted from the equivalence boundary. | Reject the three-terminal transformation when a fourth connected node is present. | Circuit designer. |
| Room-temperature equivalence is assumed to persist under unequal self-heating. | Recalculate with supported operating-state resistance and verify terminal behavior after thermal settling. | Electrical and thermal validation owners. |
System integration decisions
- Establish genuine three-terminal equivalence at the specified resistance state before comparing internal stress.
- Calculate each physical resistor's voltage and power under the same external terminal conditions.
- Keep the star's internal center separate from the three accessible terminals; exposing that center changes the network boundary.
Keep the equivalent circuit and the physical resistor map together
An equivalent network preserves the relationship between terminal voltages and terminal currents within its model. It does not preserve every internal branch current. That distinction matters when a custom resistor network is rearranged to suit a ceramic layout, a different resistor geometry or a manufacturing constraint. The customer may see unchanged signal behavior while one printed element receives more voltage or a larger share of the total heat.
The output is two linked records: the external electrical equivalence and the internal element stress under the intended operating states. This is different from correcting a loaded divider, where the terminal behavior changes because another load has been added. It is also different from reconnecting unchanged heater resistors between three-phase star and delta. Here the resistor values are transformed specifically to preserve the three-terminal behavior.
Confirm that the center node is genuinely internal
Label the external terminals A, B and C. In the star version, resistors RA, RB and RC connect those terminals to one internal junction N. In the delta version, resistors RAB, RBC and RCA connect each external terminal pair directly. The equivalence assumes that N has no additional electrical connection: it is not a ground, diagnostic port, clamp destination or hidden test load.
Changing the voltage applied at external terminal C is an ordinary operating-state change and is allowed within the model. Connecting something new to the star center N is not. Keep those nodes distinct on the drawing. A thermally attached but electrically insulating support is not an extra circuit terminal, although it can change the thermal behavior and therefore the resistances in operation.
Transform the values rather than reconnecting the same resistors
For positive, constant star resistances, form the sum of their three pair products. Divide that sum by the star arm opposite each delta side to obtain its equivalent resistance. The result generally contains three different values; a rule derived only for equal resistors is not enough for an asymmetric network. Retain adequate numerical precision before rounding to realizable values.
As an assumed example, let RA be 1 kΩ, RB 2 kΩ and RC 3 kΩ. The equivalent delta values are RAB = 11/3 kΩ, RBC = 11 kΩ and RCA = 5.5 kΩ. These are calculated circuit values, not a proposed product family. Rounding 11/3 kΩ to an available nominal value introduces an electrical error that needs its own budget; the exact equivalence used below assumes the unrounded value.
S = RA RB + RB RC + RC RA; RAB = S/RC; RBC = S/RA; RCA = S/RB
- RA, RB and RC: star-arm resistances from external terminals A, B and C to internal junction N, in Ω.
- S: sum of pair products, in Ω².
- RAB, RBC and RCA: delta resistances between the indicated external terminal pairs, in Ω.
Positive linear resistances at one defined state; exactly three external terminals and an electrically unloaded star center. Parasitic reactance and nonlinear or changing material behavior are outside this constant-DC model.
An open third terminal still permits internal delta current
First hold A at 6 V and B at 0 V, with external terminal C left open. In the star network, the 1 kΩ and 2 kΩ arms carry 2 mA in series. Junction N and terminal C are both at 4 V, so the 3 kΩ arm carries no current. The star elements dissipate 4, 8 and 0 mW, respectively; total input power is 12 mW.
The equivalent delta also draws 2 mA from A, and its open terminal C is also at 4 V. However, the delta has an internal path from A through C to B. Its RAB element dissipates approximately 9.818 mW, RCA 0.727 mW and RBC 1.455 mW. The total remains 12 mW. An externally open terminal means zero net external current at that node, not zero current in every resistor attached to it.
| Physical element | Resistance | Voltage magnitude | Power |
|---|---|---|---|
| Star RA | 1 kΩ | 2 V | 4.000 mW |
| Star RB | 2 kΩ | 4 V | 8.000 mW |
| Star RC | 3 kΩ | 0 V | 0 mW |
| Delta RAB | 11/3 kΩ | 6 V | 9.818 mW |
| Delta RBC | 11 kΩ | 4 V | 1.455 mW |
| Delta RCA | 5.5 kΩ | 2 V | 0.727 mW |
Use another operating state before ranking the two layouts
Now hold A and B at 0 V and external C at 6 V. For the same star resistors, the internal junction is at 12/11 V, approximately 1.091 V. The star powers are approximately 1.190 mW in RA, 0.595 mW in RB and 8.033 mW in RC. In the delta, RAB has no voltage, while RBC dissipates 3.273 mW and RCA 6.545 mW.
Both networks still absorb the same total, approximately 9.818 mW, and draw the same terminal currents. Yet the largest individual power is now higher in the star, whereas it was higher in the delta in the first state. There is no topology-wide winner based only on total watts. Compare the states the real source and receiver can impose, including valid startup conditions, without inventing physically impossible combinations of independently quoted voltage limits.
Recover internal voltages from each original physical topology
A circuit simulator may reduce a network to an equivalent form while solving its external behavior. Do not read an equivalent resistor's power as though it belonged to one original printed feature. Keep the original netlist for each proposed construction and solve its internal nodes under the same terminal conditions. For the star, the internal voltage is the conductance-weighted average of the three external potentials.
Once the physical node voltages are known, each element's power is its own voltage difference squared divided by its own resistance. Sum these powers and compare them with the signed terminal power entering the network. That closure should hold independently for both versions. It catches an omitted internal branch while preserving the key distinction: equal totals are a conservation check, not proof of the same spatial heat generation.
VN = (VA/RA + VB/RB + VC/RC)/(1/RA + 1/RB + 1/RC); Pe = (Vp − Vq)²/Re
- VA, VB and VC: external terminal potentials relative to one common reference, in V; VN: internal star-center potential, in V.
- RA, RB and RC: the three positive star resistances, in Ω.
- Vp and Vq: endpoint potentials of one actual physical resistor; Re: that element's resistance, in Ω; Pe: its dissipated power, in W.
Constant linear DC resistances. Floating external nodes must first satisfy zero net external current; their voltage is solved rather than assigned arbitrarily.
Map element stress to the printed construction
Attach each calculated power and voltage to a real printed resistor identifier, not merely a location on the equivalent schematic. Include its active geometry, terminations, trim region and thermal surroundings. Two elements with equal resistance can have different area and heat-removal paths; a higher milliwatt number alone does not determine which has the highest temperature.
Review the element voltage separately from its power. In the first example the delta's A–B element supports 6 V, while the largest star-arm voltage is 4 V. No voltage capability follows from those illustrative values. The actual film system, geometry, adjacent conductor potentials and protection construction need drawing-specific assessment. Do not copy the original element's acceptance merely because the substitute preserves terminal resistance.
Recheck equivalence when self-heating changes individual resistance
The exact transformation applies to the resistance values used in the calculation. If the two physical layouts develop different element temperatures, their resistances may move differently. A transformation that was exact during low-power inspection may then cease to match in the energized state. Obtain material-appropriate resistance behavior rather than assuming a universal temperature coefficient for printed thick-film resistors.
Use the predicted local losses with a suitable thermal model or measured installed temperatures, update the element resistances, and check the terminal relation again where the change matters. This is not a guarantee that a particular topology is unstable or unsuitable. It is a reason to keep low-power equivalence and operating-state verification separate. Frequency response, thermal noise under unequal temperatures and fault behavior require additional analysis when relevant; they are not certified by the DC substitution.
Approve a substitution with an element-level comparison, not a black-box pass alone
Provide both full schematics, exact transformed values, the external terminal map and a state-by-state internal voltage/power table. Keep original resistor identifiers linked to the corresponding physical drawings. If a value is rounded, trimmed or implemented using several printed bodies, recalculate the realized network instead of assuming it remains the ideal mathematical transformation.
Validate the external function and installed thermal behavior without adding an unmodeled probe load to the star center. Preserve the temperature and excitation state of each observation. The practical acceptance decision is whether the actual replacement meets both the required terminal behavior and its own internal electrical and thermal limits. A supplier can review a custom ceramic network against this package; matching a low-power black-box reading does not by itself qualify a new internal construction.
Send both network topologies and their internal stress tables
Include the physical element map as well as the required terminal behavior.
- Original star/delta schematics, external terminals and any center-node connections.
- Exact and realized resistor values with the operating resistance assumptions.
- Relevant terminal drive/load states and per-element voltage, current and power.
- Printed geometry, thermal attachment and separate electrical/thermal acceptance requirements.
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