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A liquid-level card can be protected across its printed face yet remain vulnerable where terminals cross a housing or protective boundary. Leakage is governed by the complete seal interface: terminal finish, ceramic edge, adhesive or elastomer, housing geometry, pressure, capillary gaps and electrical potential. An immersion result without path localization cannot show whether current crossed the seal, the fixture or an exposed card surface. The engineering method combines a physical ingress map with guarded electrical measurements at named nodes.
Key design decisions
- Identify every seal boundary and electrical node reachable from liquid.
- Choose pressure, temperature, orientation and bias that represent the reviewed state.
- Use witness regions or segmented measurements to localize leakage.
Map the liquid path from exterior surface to electrical node
Section the interface conceptually through housing, terminal, sealant, substrate edge and protective layer. Mark menisci, gaps, overlaps and termination edges. State which surfaces are wetted and whether pressure or thermal cycling drives liquid inward. A bulk insulation path through ceramic differs from a surface path along residue or an adhesive interface. Include fixture seals, feedthroughs and cable ends so laboratory ingress is not attributed to the product.
Represent each suspected path as a node-specific conductance
Measure or bound resistance from each terminal to return, excitation, neighboring channels and housing reference. For multiple paths, solve a conductance matrix rather than using the lowest insulation number everywhere. Bias polarity and node voltage influence current.
I_k=Σ_j G_kj(V_k-V_j); V_error=H(I_1,I_2,...)
- G_kj is leakage conductance between physical nodes k and j.
- V_k and V_j are their biased potentials during exposure.
- I_k is net unintended current at node k.
- H is the actual receiver-circuit relationship converting leakage currents to error.
A steady exposure state; capacitance, polarization and time-varying fronts are retained separately.
Calculate an output-to-return leakage example
For illustration, a 5 V-referred output node has 50 kΩ source impedance and would read 3.0 V unloaded. A 500 kΩ seal leakage to return produces approximately 2.727 V before receiver loading, a −273 mV shift. A leakage path of the same resistance to excitation moves the node in the opposite direction and requires a different calculation. These values are not design limits. They show why terminal identity and path endpoint are essential to any remaining-margin statement.
Define ingress drivers and observation timing
Record liquid composition, conductivity, temperature, pressure, immersion depth, orientation, agitation, duration and electrical bias. Include thermal or pressure cycles only as specified by the application plan. Measure during exposure where safely possible, immediately afterward, and through defined recovery. A final dry reading can miss a temporary conductive bridge. Conversely, surface wetting outside the intended seal boundary should not be mislabeled internal ingress without localization evidence.
| Evidence | Controlled detail | Decision |
|---|---|---|
| Physical section map | Seal overlaps and node locations | Propose credible paths |
| Guarded leakage channels | Node pairs, bias and time | Localize conductance |
| Exposure state | Liquid, pressure and orientation | Bound applicability |
| Connected output | Receiver and thresholds | Calculate functional consequence |
Use guards, dyes or sectioning without confusing their purposes
Guard electrodes and separate terminal measurements can distinguish surface fixture leakage from current entering the card. Tracer dyes or imaging may reveal a physical front but can change wetting and are not direct electrical evidence. Cross-sectioning is destructive and should use allocated specimens after live measurements. Compare blank fixtures and sealed dummies. A visual path without measurable node current may still matter later, while current without visible dye may follow a thin film below detection.
Review cracks, adhesion gaps and terminal movement separately
Terminal insertion force, thermal expansion and harness loads can open an interface or crack a brittle region. Sealant shrinkage or poor wetting creates another mechanism; contamination can make an intact geometric path conductive. Pattern timing and location help discriminate them. Repeat leakage while monitoring terminal displacement and card reference. Do not increase seal material or cure blindly: a stiffer seal can transfer more stress to ceramic, and additional coverage can interfere with contacts or processing.
Validate path resistance and connected-circuit effect together
Before liquid testing, insert safe known shunts between proposed node pairs and verify that instrumentation and receiver respond as modeled. Run blanks, unexposed controls and sealed specimens under the controlled sequence. Correlate leakage current, output and physical observations on a common timeline. Replication and acceptance depend on application risk. Pressure, chemicals and energized liquids require an authorized facility procedure; this method does not supply universal test limits.
Control the seal boundary across card and housing drawings
Release terminal material and geometry, card edge and protective coverage, seal material and overlap, housing support, allowed loads, wet side, dry side and electrical nodes. Specify exposure and leakage measurement conditions. ChipSimple can review drawing-defined card features and agreed specimen interfaces, while the customer owns housing seal design and system qualification. Reopen after terminal, seal, housing, liquid, pressure, bias, glaze or assembly-load changes.
Close the remaining implementation and validation risks
Compare the lowest controlled leakage resistance with the resistance that would consume receiver margin, including measurement uncertainty and position-dependent sensor impedance. Do not label their ratio a lifetime factor because ingress need not progress linearly. If no current is detected, report the instrument boundary and exposure state rather than infinite insulation. Evaluate worst credible node voltage; a seal between equal-potential conductors can appear benign until another mode changes bias. Production controls may include terminal dimensions, surface preparation, dispense geometry, cure records and gross-leak screens, but each must connect to a failure mechanism. A pressure screen may find open paths without predicting slow capillary wetting. Trace sealant lot, mix, open time and assembly delay. Retain validation specimens for sectioning after intact electrical measurements.
Complete the page-specific release closure
Seal verification should also challenge assembly variation that changes the path: terminal offset, permitted housing gap, dispense location and cure condition. Select combinations from the engineering risk assessment rather than silently testing nominal parts only. Measure dry insulation before exposure so pre-existing contamination is visible. During recovery, avoid moving liquid through connector cavities in a way unlike service. If a destructive section reveals a void, relate its location to the recorded leakage node and time; one void does not prove that it conducted, and an intact section does not exclude a path elsewhere.
Review edge wicking separately from terminal feedthrough leakage. Orient specimens so gravity and hydrostatic head are known, and include a blank card edge where it helps identify fixture paths. Record the first detection time, not only the final current. A delayed onset can guide localization but is not a universal service-life model. Preserve all node voltages needed to recalculate functional effect after threshold revisions.
Provide the terminal cross-section and liquid exposure boundary
Leakage-path review needs the housing seal and card nodes in the same package.
- Terminal, ceramic, housing and seal drawings with wet and dry sides.
- Liquid identity, conductivity, pressure, temperature, orientation and timing.
- Electrical node map, bias, receiver and leakage measurements.
- Allowed output error, structural loads and validation ownership.
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