Ceramic Sensor Acquisition: Budget Random Sampling Jitter Before Tightening Resistors

System boundary

A ceramic passive sensor-conditioning network feeding a clocked converter. The task is random sampling-time uncertainty on a changing analog input; hold-capacitor leakage, PWM exclusion windows, analog settling and converter distortion have separate models.

Integration interfaces

Integration risks

Separate when sampling occurs from how consistently it occurs

A fixed delay shifts the effective sampling instant relative to a clock reference. Random sample-to-sample changes in that delay are a different quantity. A stable delay can affect alignment with another channel or a system event without creating the same noise as random timing variation. Record aperture delay, channel skew and RMS timing uncertainty separately rather than placing every time specification into one root-sum-square calculation.

Likewise, a converter's finite acquisition interval is not automatically its jitter. The actual hardware defines how a voltage is captured. This discussion uses a small random displacement of the effective sampling instant to isolate one mechanism. It does not certify that the input settled, that a PWM disturbance was avoided or that the held voltage remained unchanged afterward.

Translate timing variation through the input slope

For a small timing displacement delta t, a first-order expansion gives voltage error approximately equal to the local derivative dv/dt multiplied by delta t. The same timing uncertainty therefore matters more on a steep part of a waveform. A nearly constant input can hide this mechanism; a clean DC resistor-ratio result does not establish dynamic acquisition accuracy.

The expansion requires the timing displacement to be small relative to the waveform's relevant time scale. Use a finite physical waveform, not an ideal discontinuous step with an undefined instantaneous slope. Random timing can interact with deterministic clock modulation or signal phase, so distinguish the statistical model used for RMS estimates from a worst-case local-slope bound. They answer different acceptance questions.

Derive the jitter-only sine-wave limit

For v(t)=A sin(2 pi f t), the slope has amplitude 2 pi f A. If small zero-mean timing errors are independent of signal phase and the observations cover the phases appropriately, RMS error is approximately 2 pi f A sigma-t divided by square root two. The signal RMS is A divided by square root two, so amplitude cancels from the signal-to-jitter-noise ratio.

The resulting jitter-only SNR is minus twenty times log base ten of 2 pi f sigma-t. Here f is the analog input frequency, not the sampling clock frequency or a software display cadence. A smaller input amplitude lowers the absolute jitter-related voltage error but does not improve this idealized ratio. Other additive voltage noise changes that conclusion for total measured SNR.

Compare dynamic errors before changing a resistor grade

Assume a one-volt-peak sine wave and 100 nanoseconds RMS effective timing uncertainty. At 1 kilohertz, the calculated jitter-related error is approximately 0.4443 millivolt RMS and jitter-only SNR is approximately 64.04 decibels. At 10 kilohertz, error becomes approximately 4.443 millivolts and SNR falls to approximately 44.04 decibels. The resistor network did not change between these calculations.

For comparison, a fixed 100 nanosecond delay at 10 kilohertz is a phase displacement of 0.36 degree. It does not produce random noise in this ideal model if it is genuinely constant. Confusing that fixed delay with 100 nanoseconds RMS jitter would predict the wrong symptom and can send the corrective action to the wrong component.

Allocate the clock contribution after accounting for converter jitter

For an illustrative jitter-only target of 80 decibels at 10 kilohertz, total RMS timing uncertainty must be no more than about 1.592 nanoseconds under the sine model. If a separately justified converter aperture contribution is 0.8 nanosecond RMS and the external clock contribution is independent, the external allocation is the square root of the total allowance squared minus 0.8 nanosecond squared: approximately 1.376 nanoseconds RMS.

Do not subtract the RMS values directly. Variances add for independent zero-mean contributors; correlated contributions require covariance, and unknown dependence cannot be assumed favorable. Use compatible jitter definitions and relevant integration bandwidths. Peak-to-peak timing from one capture is not an RMS specification, and an oscillator period-jitter value is not automatically the effective sampling-time uncertainty required by this calculation.

Keep a separate budget for non-timing errors

Independent RMS voltage contributions combine in variance at a common referred node. Meeting an 80 decibel jitter-only target does not leave the entire same allowance available to resistor noise, converter noise and interference. If two independent mechanisms each consume the full permitted variance, their combined RMS error exceeds the allocation. Perform the combined budget before selecting a passive tolerance upgrade.

Distortion and deterministic clock-related spurs are not interchangeable with broadband random noise. An SNR extraction that excludes harmonics answers a different question from SINAD. Likewise, digital averaging may change the reported variance without proving that every captured instantaneous value was accurate. Retain the acquisition and processing definitions when comparing a new resistor construction or a different sampling configuration.

Use controlled frequency and clock comparisons to test the hypothesis

Compare appropriate analog input frequencies at a controlled amplitude while holding the acquisition configuration fixed. A timing-related contribution should scale with slope within the model's valid range, but worsening high-frequency performance alone is not proof of jitter. Front-end bandwidth, distortion, input-source noise and incomplete acquisition can create competing signatures. Characterize those boundaries rather than assigning every frequency-dependent error to the clock.

The signal generator and clock distribution can add uncertainty to the experiment. When changing a clock source, keep relevant analog paths and processing unchanged and record the new timing definition. A shared source can create correlations that alter the observed result. The validation record must describe the whole test chain, not claim the converter's intrinsic aperture performance from an uncontrolled laboratory setup.

Attach the dynamic timing allocation to the ceramic interface drawing

Provide the actual sensor waveform range, passive transfer, converter mode, sampling clock path and required dynamic accuracy. Separate static resistor-ratio error, fixed alignment delay, random timing uncertainty and additive voltage noise. Identify the owner responsible for each allocation and state the analog conditions under which the combined measurement has been demonstrated.

ChipSimple can review the drawing-defined passive conditioning network, while the acquisition designer validates sampling and clock behavior. A resistor change is justified when its measured contribution limits the intended result, not merely because the overall waveform looks noisy. Preserve the timing calculation and test conditions so a later clock, converter or firmware substitution cannot silently inherit an unsupported dynamic accuracy claim.