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A power module may place an auxiliary passive sensing function near a ceramic power substrate, but proximity does not make the two circuits interchangeable. Direct-bonded copper is commonly selected for high-current interconnection and heat spreading; a thick-film sensing pattern is a separate functional network with different conductor geometry, current level, terminals, insulation questions and measurement purpose. The sensed coordinate also depends on attachment and heat flow, not only on artwork location. Integration must keep power current, switching fields, sensing excitation, reference routing, isolation, mechanical stress and diagnostic ownership explicit. ChipSimple may review a drawing-defined thick-film ceramic sensing circuit. The module owner remains responsible for semiconductor operation, DBC design, insulation coordination, cooling, protection, safety and complete module qualification.
System boundary
The boundary includes semiconductor devices, die attach, DBC ceramic and copper, power terminals, auxiliary thick-film substrate or pattern, its attachment, sense terminals, wire bonds or connectors, baseplate, thermal interface, cooler, enclosure, gate drive, sensing excitation, acquisition, filtering, diagnostics and protective controls. ChipSimple scope is limited to the reviewed thick-film drawing and agreed passive interfaces.
System integration decisions
- Assign separate schematics, nets and physical boundaries to power routing and auxiliary sensing.
- Define which temperature or electrical coordinate the passive pattern is intended to represent.
- Close insulation, clearance and reference routing at the assembled-module level.
- Validate sensing error during real switching and thermal gradients, not only on a quiet bench.
Separate power transport from auxiliary measurement at the architecture level
Create distinct schematics, net names, connector pins, current limits and design rules for the DBC power path and auxiliary thick-film network. Identify every intentional connection between their reference domains. Power routing must be reviewed for semiconductor current, commutation loop and fault energy; the passive sensing circuit is reviewed for its measurement excitation and output. Do not infer that printed conductors can carry DBC load because both are located on ceramic. Likewise, do not count DBC copper geometry as part of the sensing transfer unless the module circuit deliberately includes it and the full interaction is analyzed.
Define the sensed quantity and its physical coordinate
State whether the passive pattern is intended to indicate local ceramic temperature, baseplate condition, an interface trend or another bounded quantity. Mark the coordinate and area on the mechanical drawing, including distance and layers between heat source and sensing element. Semiconductor junction temperature, case temperature, DBC surface temperature and auxiliary-substrate temperature are not synonyms. Establish an independent reference method for validation and identify operating modes in which the correlation is valid. The system owner chooses protection or control use from qualified module evidence; component resistance alone does not establish that use.
Map heat from semiconductor sources to the sensing pattern
Draw die, die attach, DBC copper, ceramic, any auxiliary substrate and bond, baseplate, interface material and cooler as a spatial network. Include neighboring devices and asymmetric cooling. A sensor close in plan view can be thermally distant when a low-conductance joint or copper boundary redirects heat. Record attachment footprint and thickness tolerances because they change both response time and steady offset. Use thermal modelling to select test coordinates, then verify with instrumented assemblies. The model boundary and material inputs must accompany any inferred relationship.
Represent sensing lag as a bounded dynamic relationship
A single-mode expression can screen whether delay is important before a richer model is fitted.
T_s(t)=T_0+K P[1-exp(-t/tau_s)]; e_T(t)=T_ref(t)-T_s(t)
- T_s is the auxiliary sensing coordinate represented in temperature units after calibration.
- T_ref is the independently measured module coordinate of interest.
- P is the stated loss or heating input, K is local sensitivity and tau_s is an identified time constant.
The local system is approximately linear for the examined step; multiple dies, switching loss changes, nonlinear cooling and spatial gradients require measured multi-mode treatment.
Calculate an illustrative transient observation gap
Suppose an approved characterization step ultimately changes the sensing coordinate by 30 K and the identified time constant is 8 s. After 4 s, the first-order sensor-coordinate rise is about 11.8 K, leaving 18.2 K of its eventual change unobserved at that instant. These figures explain timing only; they are not module ratings or ChipSimple sensing performance. The relevant reference coordinate may move faster or slower than this example. Protection decisions must use measured worst-case correlations and independent safeguards selected by the module owner.
Review insulation and spacing in the assembled electric field
Provide power-net voltages, switching nodes, reference domains, conductor elevations, ceramic and coating stack, clearances, creepage paths, edges, fasteners and contamination environment. The auxiliary circuit can cross a strong field even while drawing little current. Coating presence does not automatically establish an insulation rating, and a ceramic material name does not close the complete surface path. Insulation coordination, partial-discharge questions where applicable, production cleanliness and regulatory requirements remain system-level responsibilities supported by appropriate evidence. Never publish an isolation value without the specific construction and validated test basis.
Specify excitation, reference and acquisition behavior
Document sensing topology, resistance range by drawing, excitation source and tolerance, permitted self-heating, terminal assignment, harness, input impedance, common-mode range, protection components, analogue bandwidth, ADC reference, sample timing and digital filter. Measure at the sensing terminals and acquisition input during development. Ratiometric conversion can reduce source variation but cannot remove reference displacement, leakage, switching pickup or thermal lag. Diagnostic pull resistors can load a passive divider and bend its transfer. Recalculate the installed network whenever the input module or protection path changes.
Challenge the sensing path during representative switching states
Acquire raw sense voltage, excitation, power-stage voltage and current, gate state and selected temperatures on a synchronized timebase with suitable measurement safety. Compare quiet, switching, load-transition and fault-response intervals that the system owner permits. Change acquisition phase or bandwidth only as a controlled diagnostic, not to make an unexplained disturbance disappear. A spike locked to a switching edge suggests coupling or reference behavior; a slower shift following calculated loss may be thermal. Confirm cause with routing, shielding, grounding or thermal experiments before changing calibration.
Trace assembly force through both ceramic structures
Show supports, fasteners, clamps, baseplate flatness, thermal-interface material, terminal loads and assembly order. The DBC and auxiliary ceramic may have different thickness, stiffness and attachment footprints, so one clamping approach can load them unequally. Prevent wire bonds, printed pads or the auxiliary substrate from becoming alignment stops. Inspect seating and contact evidence before and after torque or cure. Include thermal expansion and service replacement in the review. A successful electrical bench test does not qualify ceramic stress, joint integrity or vibration behavior.
Keep evidence packages distinct but connected
This allocation avoids transferring a power-substrate claim to the auxiliary circuit or vice versa.
| Evidence block | Minimum record | Owner |
|---|---|---|
| Power routing | DBC stack, current path, switching and fault energy | Power electronics |
| Thermal correlation | Heat sources, stack, cooling and reference temperatures | Thermal engineering |
| Auxiliary circuit | Pattern, resistance targets, pads and terminals | Drawing review |
| Insulation system | Domains, spacing, materials, environment and tests | Insulation authority |
| Acquisition | Excitation, reference, loading, bandwidth and diagnostics | Controls hardware |
| Protective action | Limits, plausibility, interruption and safe state | System safety |
Diagnose thermal, electrical and mechanical signatures separately
A resistance shift that follows independently measured local temperature during quiet and switching operation supports thermal interpretation. A high-frequency error synchronized with switch edges directs investigation to capacitive or inductive coupling, common mode and reference routing. A step appearing after clamp assembly suggests contact, strain or terminal loading. A slow relationship change after thermal cycling can involve attachment or cooling as well as the passive pattern. Preserve raw acquisition, power state, reference temperatures and assembly condition. Correlation narrows the investigation but does not replace inspection or controlled reproduction.
Validate the auxiliary signal inside the complete module boundary
Begin with drawing inspection and low-energy passive characterization. Then use an integrator-approved module setup to correlate the auxiliary output with calibrated reference temperatures across steady loads, controlled transitions, cooling extremes and relevant switching states. Include attachment and clamp tolerances. Record raw and converted signals, power loss evidence and protection status. Exercise open, short and implausible responses under the owner’s safe procedure. ChipSimple review cannot approve semiconductor safe operating area, DBC reliability, converter control or complete module safety.
Reopen correlation after any power, thermal or sensing revision
Review changes to semiconductor, switching frequency, gate strategy, DBC artwork, copper thickness, die attach, auxiliary pattern, substrate, bond, baseplate, cooler, clamp, insulation, terminals, harness, excitation, ADC, filtering or firmware. Tie correlation data to complete module configuration. Equal nominal power does not preserve loss location, and equal steady baseplate temperature does not preserve transient junction behavior. Transfer evidence only across demonstrably unchanged paths; repeat affected thermal, interference, insulation and diagnostic checks.
Keep module performance claims with the qualified system
This guide does not claim DBC capability, power-current capacity, junction-temperature accuracy, isolation rating, switching immunity, lifetime, safety integrity or regulatory compliance. The calculation illustrates a dynamic method only. Actual thick-film materials, geometry, resistance, pads and terminals remain by drawing and application review. A complete RFQ must distinguish power and auxiliary networks and supply the thermal stack, reference coordinate, acquisition circuit and validation ownership before the sensing requirement is released.
Provide separate power and auxiliary sensing boundaries
Review requires the module stack, electrical domains and intended sensing correlation.
- Module schematic, DBC construction, semiconductor layout, switching states, current paths and fault-energy ownership.
- Auxiliary sensing drawing, substrate, pattern, target resistance or transfer, pads, terminals and attachment.
- Heat-source map, die and baseplate stack, cooler, interface materials, clamp and intended reference coordinate.
- Power-domain voltages, insulation system, clearances, environment, excitation, harness, receiver and ADC timing.
- Operating modes, calibrated thermal references, interference tests, diagnostics, protection and revision-controlled acceptance.
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