Relaxation Oscillators: Calculate Both Half-Cycles from the Actual Output Levels

System boundary

A comparator with positive-feedback threshold resistors, an RC timing path and a defined bias reference on or connected to a ceramic hybrid. The model predicts ideal switching intervals, not complete oscillator accuracy, startup reliability or comparator performance.

Integration interfaces

Integration risks

Name the timing node and threshold node separately

Consider a comparator whose inverting input senses capacitor voltage and whose noninverting input receives positive feedback. The output charges or discharges the capacitor through timing resistance R. Define the feedback threshold as a weighted average of output and a stiff reference: fraction a of output plus one minus a of reference voltage. This explicit two-resistor threshold model avoids assuming a particular timer IC or internal threshold network.

Record actual output levels H and L under the installed load. A push-pull output, an open-collector output with a pull-up resistor and a heavily loaded logic interface can produce different charging paths. The first-order calculation below assumes the output can be represented by fixed H and L during each interval. If its impedance materially changes the timing current, include that impedance rather than treating the unloaded logic levels as the drive source.

Recompute both thresholds when the output levels move

With output high, the threshold is VH equal to aH plus one minus a times Vref. With output low, it is VL equal to aL plus one minus a times Vref. The capacitor rises from VL toward H until it reaches VH, then falls toward L until it reaches VL. The ordering L below VL below VH below H is required for the two ideal crossings.

Measure the threshold-node voltage in both output states or calculate it using the actual divider resistances and loading. Comparator input current, reference impedance and any other connected branch can change the weighted average. An output waveform alone does not identify those errors. Keep the threshold ratio separate from timing resistance even when both are printed within one ceramic resistor network.

Calculate charging and discharging as different intervals

During the high interval, the capacitor approaches H exponentially from VL. During the low interval, it approaches L from VH. Solving the two crossing equations gives the logarithms below. Their sum is the ideal period and their ratio determines the high-output duty fraction. Do not assume equal half-cycles unless the actual voltages and resistance paths support that symmetry.

These equations describe the analog capacitor crossings. Comparator propagation, output transition time and any additional blanking or logic delay affect the measured output period. At sufficiently short RC intervals, those terms can be comparable to the nominal timing. Keep them separate so a discrepancy does not automatically become a request to alter the printed resistor's value.

Recognize the symmetric case where swing reduction cancels

If Vref is exactly the midpoint of H and L, the two intervals become equal. Each is RC times ln[(1+a)/(1−a)]. The absolute output swing cancels because both the drive excursion and the feedback thresholds shrink together. A symmetric reduction in high and low swing therefore does not change this ideal period when the reference follows their midpoint and all other assumptions remain valid.

For a equal to one third and RC equal to one millisecond, each interval is ln(2) milliseconds, about 0.693147 millisecond. The ideal frequency is about 721.348 hertz with 50 percent duty. Output pairs of 5/0 V and 4.5/0.5 V both give that result with a 2.5 V reference. This is a mathematical cancellation in the stated topology, not a claim that real output loading has no effect on an oscillator.

A fixed reference can break that symmetry

Keep the reference at 2.5 V and the feedback fraction at one third, but assume the high output falls to 4.0 V while the low output remains 0.5 V. VH becomes 3.0 V and VL becomes approximately 1.833333 V. The high-interval logarithm is ln(13/6), approximately 0.773190, while the low-interval logarithm is ln(15/8), approximately 0.628609.

With the same one-millisecond RC product, the period becomes approximately 1.401799 milliseconds and frequency about 713.37 hertz. High-output duty is approximately 55.16 percent. The frequency change is relatively small compared with the duty movement. Measuring only frequency would miss that asymmetry; changing R rescales both intervals together and cannot independently restore the desired duty fraction.

Use period and duty together to locate the controlling change

A useful oscillator record contains R, operating-state C, H, L, VH, VL and both intervals. Compare those quantities before and after a load, supply or temperature change. If the normalized voltage ratios stay unchanged while both times scale together, the RC product is a plausible contributor. If one interval changes more strongly, inspect the linked output and threshold states first.

Use the following comparisons to choose a targeted experiment. Keep the signal amplitudes within the selected comparator's input limits and account for probe loading at the capacitor and threshold nodes. Adding a probe can change a small timing capacitance or load the divider, so an apparently improved frequency after probing needs the same circuit review as any other extra component.

Check the reference and output load as part of the oscillator

A reference derived from the supply may not track the actual midpoint of the loaded high and low output levels. Conversely, a reference that deliberately follows that midpoint has its own circuit dynamics and loading requirements. State the implementation instead of claiming supply-independent frequency from a familiar formula. Include output fan-out and the capacitance of the receiving logic input in the verification configuration.

Compare a lightly loaded output with the intended installed load, then repeat at the required supply and temperature boundaries. Separate resistor TCR, capacitor movement and comparator behavior rather than assigning the complete frequency coefficient to the printed network. A ratio-trimmed feedback divider and a trimmed timing resistor perform different jobs; preserving only one relationship may leave the other outside its requirement.

Specify the network from two timing requirements

Provide the required frequency and duty interval, the threshold topology, reference source and actual output load. Include the allowed contribution from the timing resistor and from the feedback ratio separately. If trimming is intended, state which element can change and whether the resulting correction must hold across several operating states. A room-temperature frequency adjustment alone does not define a complete oscillator acceptance plan.

Verify startup, stable cycling and relevant state changes with the assembled comparator and capacitor. Retain raw capacitor/threshold/output traces and calculated residuals. The resulting handoff tells the printed resistor supplier what relationships to control while leaving active-device timing, logic loading and complete oscillator performance with the electronics design that actually determines them.