Sample-and-Hold Sensor Inputs: Set the Hold-Time Limit from Leakage and Droop

System boundary

Sensor input, sampling switch, retained capacitor, connected resistor paths and receiving buffer. This page allocates switch-open retention rather than track-mode acquisition.

Integration interfaces

Integration risks

Define the retained node and its connected paths

Identify the holding capacitor, the open sampling switch, the output buffer and every resistor connected to the held node. A printed input network upstream of an open switch may determine acquisition but no longer directly control the retained voltage. A resistor still connected downstream can discharge the capacitor throughout hold. Draw the actual switch state instead of carrying the track-mode circuit unchanged into the retention calculation.

The stored quantity is the capacitor voltage at the capture event, not the continuously changing sensor input afterward. A valid hold specification therefore states an error relative to that captured value. If the application instead requires the latest physical sensor value, a perfectly retained old sample can still be stale. Data age and charge retention are separate requirements with different remedies.

Translate hold-node current into voltage change

For an ideal holding capacitor with approximately constant net current, the voltage change is delta V = Inet t/C. Inet is signed current entering the capacitor in amperes, t is elapsed hold time in seconds and C is effective capacitance in farads. Positive current raises the stored voltage under this sign convention; current leaving it lowers the voltage.

The net current can include switch leakage, buffer input current, capacitor leakage and surface or fixture paths. Their signs may differ, but do not claim permanent cancellation from one room-temperature observation. Use applicable component limits and operating states to establish the allocation. When only magnitude bounds are known, their sum gives a conservative bound; combining independent statistical quantities requires a justified statistical model.

Convert the allocated error into a latest use time

Assume an illustrative 10 nF holding capacitor and a bounded net-current magnitude of 1 nA over the evaluated voltage and temperature interval. The voltage-change rate is 0.1 V per second, or 0.1 mV per millisecond. A 10 mV allowance allocated entirely to this effect permits at most 100 ms under the constant-current model.

Now allocate 2 mV to initial switching and settling error and 3 mV to other worst-case contributions, leaving only 5 mV for subsequent droop within the same 10 mV total bound. The allowed hold duration becomes 50 ms. Starting the timer after a convenient software delay does not recover that spent retention time. The time reference must remain tied to the actual capture event.

Use an exponential model for a defined resistive path

A known resistance to a fixed potential does not draw a constant current as the held voltage changes. For a resistance R to reference Vr, the ideal voltage is V(t) = Vr + (V0 minus Vr) exp(-t/(RC)). V0 is the initial held voltage; all voltages use the same reference. This model applies only if the path is reasonably linear and the capacitor can be represented by one effective value.

With an assumed 1 gigohm path to zero, a 10 nF capacitor and an initial 2 V value, the time constant is 10 seconds. After 100 ms the loss is approximately 19.90 mV. Treating that path as irrelevant because its resistance sounds large would miss the example's entire 10 mV error allowance. Other current sources can be included in the node equation, but must not be counted twice as both resistance and leakage current.

Separate the opening transient from the later slope

Opening a real switch can inject charge and cause an initial voltage step. Subsequent buffer settling can add another short transition. Measure that initial behavior separately from the slowly changing held level. A straight-line fit across a switching transient produces a misleading droop rate and cannot establish a valid earliest measurement time.

A capacitor may also retain memory of its previous voltage through dielectric absorption. A hold trace that curves or changes with the previous sample history is not fully described by one constant leakage current. Compare sequences that begin from different previous voltages. Keep feedthrough from the still-active input separate as well; the open switch does not imply that every capacitive coupling path has disappeared.

Identify which part of the timing window has failed

The useful interval begins only after the capture transient has settled sufficiently and ends when retention error exceeds its allocated limit. The following observations lead to different changes. Enlarging the holding capacitor can reduce current-driven droop, but it also changes charging requirements, so it is not a free correction.

Measure retention across voltage, time and temperature

Capture the held output at several known delays after the physical switching event, using a buffer or instrument whose loading is included in the model. A direct meter connection can create a discharge path far larger than the circuit's intended leakage. Record the effective measurement input resistance and capacitance rather than assuming that a high-impedance setting is automatically adequate.

Repeat at representative held levels and specified temperature states because component leakage and buffer behavior depend on operating conditions. Include both polarities where the application permits them. Keep a record of initial capture error, later voltage change and sample history. One slope at one voltage cannot establish a universal retention time for every channel or environmental condition.

Carry the valid hold interval into conversion scheduling

Specify an earliest and latest permitted use time relative to the capture event. The converter's actual input requirements determine whether the held voltage must remain valid through the full conversion or a shorter internal sampling interval. Translate the device documentation into the timing requirement instead of assuming all ADC architectures use the stored voltage identically.

For a ChipSimple sensor-network enquiry, provide the track and hold schematics, capacitor, switch, buffer and required voltage-error budget. Identify resistors that remain connected during hold and those isolated by the switch. Retain acquisition verification as a separate check after any capacitance change. A complete interface specification states both how the sample is obtained and how long it remains accurate enough to use.