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Adding test pads does not automatically make every buried connection testable. Coverage depends on which physical branches can influence the measurements, which independent nets are compared, and what fault the acceptance limit can distinguish. A useful test-access calculation starts with the circuit's physical connections and produces an explicit fault-to-test matrix. It separates accessible terminal count from demonstrated fault detection so a multilayer design does not acquire a misleading coverage percentage simply because most visible pads can be probed.
Key design decisions
- Preserve physical branches as well as the logical netlist; an open in a redundant internal path may leave terminal connectivity unchanged.
- List intended connections and intended isolations separately, with limits appropriate to the actual printed conductors and components.
- Record unobservable faults explicitly and assign an earlier inspection state or an additional measurement instead of silently removing them from the coverage denominator.
Keep the physical graph behind each logical net
A logical net says that its terminals should be electrically connected. It may not record every printed segment, crossover transition or parallel route that creates that connection. Retain a physical graph in which edges represent those segments and nodes represent junctions or terminal regions. Mark which nodes are electrically accessible at each manufacturing state.
For example, terminals A, B, C and D may share one logical net through three branches leaving A. If D becomes inaccessible after a dielectric layer or component is added, measurements from A to B and A to C do not directly challenge the branch toward D. The net can appear connected at the available terminals even with that branch open. The appropriate response is to expose a relevant test state or add an observable endpoint, not to rename the branch as covered.
Count a connected set of terminal checks
For n accessible terminals intended to form one connected net, n minus one pairwise checks can connect all those terminals in a test graph. A star from one terminal to every other terminal is a simple arrangement. This is a graph-connectivity count, not a claim that the instrument performs exactly that many operations or that it detects every physical fault in the conductor layout.
Consider four isolated nets with three, two, four and one accessible terminals. The connected-check counts are two, one, three and zero, totaling six. The single-terminal net cannot receive an internal continuity check from that lone access point, although it still matters for isolation testing. Record this limitation separately rather than interpreting zero required pair checks as complete physical coverage.
Ncontinuity = sum(ni - 1) for nets with ni >= 1; Nnet-pairs = M(M - 1)/2
- ni: number of accessible terminals in logical net i at the stated test stage.
- Ncontinuity: number of edges in connected pair-check trees across those accessible terminals.
- M: number of distinct logical nets; Nnet-pairs: count of unordered net pairs for a direct isolation inventory.
Counts organize a test map for a passive, unpowered network. They do not prescribe tester algorithms, quantify analog defect sensitivity or establish coverage of inaccessible branches.
Include net pairs that should remain separate
The four-net example has six unordered net pairs. A direct pair inventory makes it clear whether each pair is assigned an isolation check, deliberately grouped in a validated test, or excluded for a stated circuit reason. Check the artwork for physically adjacent conductors and overlapping layers as well as the schematic. A pair that appears distant in the logical drawing may share a small printed dielectric region.
An unintended connection is detected only when it changes a measurement beyond the chosen boundary. A continuity beep is not a useful substitute for separate low-resistance connection and high-resistance isolation requirements. Set stimulus, settling and limits for the actual construction. Do not copy a cable tester's generic resistance threshold onto a ceramic circuit with different conductor resistance, leakage sensitivity or installed components.
Build the matrix before reporting a percentage
Write a row for each specific fault under review and columns for the measurements that could distinguish it. A fault description needs its location, electrical change and relevant magnitude. A complete open, a small resistance increase and a moisture-dependent leakage path are different rows even when they occur at the same crossover. Mark a detection only when the modeled or challenged response exceeds the applicable decision uncertainty.
The following examples show why accessible-node coverage and fault coverage cannot share an unexplained percentage. A board with ten accessible points out of twelve has 83.3 percent point access. That figure says nothing about how many of its defined fault conditions will be detected. The fault matrix may expose a single inaccessible endpoint controlling an important function despite the apparently high access figure.
| Defined fault | Available measurement | Coverage interpretation | Design response if unresolved |
|---|---|---|---|
| Complete open on A-to-B branch | Resistance measured directly from A to B with alternate paths absent | Observable under the selected low-resistance limit | Challenge the program with that open condition |
| Open on hidden branch ending at D | Only A-to-B and A-to-C checks remain | Not established by these readings | Add a D-related access point or check before concealment |
| Open in one of two redundant internal routes | Terminal continuity remains through the other route | Binary continuity may not distinguish the change | Evaluate quantitative resistance sensitivity or earlier inspection |
| Bridge between two isolated nets | A defined isolation measurement between those nets | Observable only within its stimulus and resistance sensitivity | Retain pair coverage and a representative bridge challenge |
| Wrong resistor value between accessible nodes | Only a broad connectivity pattern is checked | Value accuracy is not covered | Measure the network response with component paths included |
| Leakage appearing only during exposure | A dry low-voltage end-of-line reading | Exposure-dependent behavior is not established | Assign the relevant environmental measurement separately |
Recalculate observability when components are present
A passive component can create an intended path that changes the meaning of a shorts measurement. Parallel resistors alter the resistance seen between accessible nodes, and a shorted low-value resistor can remain classified as connected by a broad threshold test. Derive the expected network response with the installed components rather than treating the finished hybrid as a bare conductor pattern.
Also check the permitted test energy. A test described as low voltage can still apply an unsuitable current or transient to a sensitive die. Review current limits, switching behavior, polarity and stored charge against the actual components. Keep high-voltage insulation procedures outside a generic continuity program unless a qualified component-aware procedure explicitly covers that assembly state.
Assign inaccessible faults to the last observable state
Build an access map after each operation that changes visibility: an added dielectric, a conductor pass, overglaze, die attachment or a housing feature. The useful intermediate test occurs after the fault-generating operation and before the relevant access is lost. Testing too early can miss damage introduced by the following operation, while testing after concealment can remove the ability to isolate its location.
Intermediate evidence does not automatically establish final integrity. Identify later operations capable of damaging the previously checked branch and choose a final functional or indirect check where needed. Keep both results connected to the same part identity. A coupon can characterize a process feature, but it cannot replace the missing endpoint of every production circuit in a claim of individual electrical coverage.
Challenge the test program with controlled faults
Use a controlled development specimen or suitable test model to introduce selected faults without altering unrelated paths. Verify the expected failure indication, affected net identification and disposition output. Include an unchanged specimen to confirm that an adjustment intended to detect one fault has not made the normal network fail systematically. Avoid using a potentially damaged customer assembly as an informal fault-injection fixture.
Retain the actual introduced condition. A conductive jumper represents a low-resistance bridge but does not simulate every leakage mechanism. Disconnecting a terminal may not reproduce a partial buried crack. The resulting challenge record should state exactly which fault and magnitude it supports, rather than extrapolating one successful demonstration into universal detection of every defect with a similar name.
Issue coverage with a stable denominator
Report the number and identities of defined faults, those demonstrated detectable, those supported only by a model, and those unresolved. Keep point access and logical-net access as separate planning statistics. If the fault list changes, retain the prior version so an apparent improvement in percentage cannot be caused simply by removing difficult rows.
The design decision may be to add a test pad, alter a route, preserve intermediate access or accept a bounded inspection limitation through the appropriate project review. State that decision beside the drawing and test-program revisions. A transparent coverage record is more useful than a large unexplained percentage because it shows exactly what can escape the chosen electrical tests and where another method must contribute.
Send the netlist and stage-specific access map
Provide the physical connections and the faults that matter so electrical coverage can be assessed before later layers remove the required access.
- Schematic, logical netlist and layer artwork showing physical branches, crossovers, vias and redundant routes.
- Probe coordinates and accessible nodes after each printing, protection and assembly stage.
- Continuity and isolation requirements, permitted test stimulus and installed component restrictions.
- Defined fault list, current test matrix, observed program challenges and any unresolved hidden-node conditions.
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