Printed resistors and networks

Thick Film Voltage Dividers: Loading Error and Input Impedance

Calculate loaded divider output, source impedance and meter-induced error, then define the receiver conditions needed for a useful resistor specification.

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Printed divider elements with connection pads. External circuit loading must be included in the divider calculation.
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A divider that has the correct resistance ratio can still deliver the wrong voltage because its receiver draws current. The receiver may be an ADC input, amplifier, protection network or simply the meter used to inspect the circuit. The first design task is to calculate the loaded transfer function. Only then is it useful to decide how tightly the printed resistors need to match and how the finished assembly should be tested.

Key design decisions

  • Include the receiver and test instrument in the equivalent circuit; an unloaded calculation is not a specification for every connected load.
  • Separate steady resistive loading from sampling-current and capacitance effects, which require time-domain information.
  • Choose total resistance by considering power, input impedance and output settling together rather than optimizing only the nominal divider ratio.

Name the top, bottom and load resistances

Call the resistor from the source to the output node Rtop, and the resistor from that node to the return Rbottom. A resistive receiver connected between the output and return is Rload. Its current adds to the current through Rbottom, so the current through Rtop is no longer the same as the current through the bottom resistor. The familiar unloaded ratio therefore cannot be used unchanged.

Draw the receiver return explicitly. If it returns to a different ground potential, the circuit has both loading and reference error. Include any meter connected during acceptance testing as another parallel branch. A test fixture that attaches a ten megohm meter to a high-impedance divider is part of the circuit, not an electrically invisible observer.

Calculate the loaded bottom leg

The bottom resistor and a linear resistive load combine in parallel. Replace them with their equivalent resistance, then apply the ordinary divider relation. This gives a simple exact DC calculation under the stated assumptions. It also shows the direction of the effect: a load to the return reduces the effective bottom resistance and pulls the output below the unloaded value.

For a hypothetical 90 kilohm top resistor and 10 kilohm bottom resistor, the unloaded transfer is 0.1. With a 100 kilohm receiver, the bottom equivalent becomes approximately 9.091 kilohms and the transfer becomes 0.091743. The output is about 8.26 percent below the intended unloaded value. Improving resistor matching to a small fraction of one percent cannot compensate for this unaccounted receiver condition.

Rbottom,eff = Rbottom Rload / (Rbottom + Rload); Vout/Vin = Rbottom,eff / (Rtop + Rbottom,eff)

  • All three resistances are positive DC resistances in ohms.
  • Vin is applied across the complete divider and Vout is measured against its return.

The source is ideal, the receiver is linear and resistive, and temperature and voltage-dependent resistance changes are excluded from this calculation.

Use output resistance to size the loading allowance

A second view replaces the unloaded divider with a Thevenin voltage source and series output resistance. For an ideal input source, that resistance is Rtop in parallel with Rbottom. The loaded-to-unloaded output ratio is Rload divided by the sum of Rload and the Thevenin resistance. This representation is useful because it directly compares the receiver with the source it is loading.

If the acceptable fractional drop is epsilon, the resistive load must be at least the Thevenin resistance multiplied by one minus epsilon and divided by epsilon. For a one percent loading allowance this is 99 times the Thevenin resistance. It is not universally 99 times the total divider resistance. Confusing those two resistances can lead to unnecessarily high dissipation or, in another topology, an inadequate input-impedance requirement.

Include the source and every measurement branch

A nonzero source resistance appears in series with Rtop when the specified input voltage is defined before that resistance. However, if Vin is measured directly at the divider input terminals, the source drop has already been included in the observed input. Define which voltage is being divided before adding an error term, or the same source effect may be counted twice.

When a receiver and meter are attached together, use their parallel combination as the output load. A reading that changes when a second instrument is connected is a diagnostic clue, not immediate evidence of a defective resistor. Perform a controlled comparison with known loads while monitoring Vin at the same terminals. If the predicted and measured loading shifts agree, the remedy belongs in the impedance allocation or test definition.

Choose a model that matches the receiver

Input impedance is not always one fixed resistance. Protection leakage may change with voltage, an amplifier contributes bias current, and a sampling converter draws charge in short intervals. The DC resistor model remains useful for the static part, but it must not be stretched to explain mechanisms with different units and time dependence.

Receiver behavior and the appropriate loading calculation
Receiver behaviorModel to includeVerification condition
A stable resistor to returnParallel RloadMeasure output after DC settling with the specified load connected
Input bias or leakage currentSigned current entering or leaving the nodeCheck relevant input voltage and temperature extremes
Input capacitanceCapacitance driven by divider output resistanceEvaluate transition and settling time, not only final voltage
Sampling inputAcquisition charge demand and switched input networkUse the converter's actual acquisition timing and driver arrangement
Additional inspection meterMeter resistance and capacitance in parallelCompare the test connection with the installed receiver

Separate settling from static accuracy

A capacitance at the output draws no continuous current in an ideal settled DC state, but it slows the response to an input change. With a suitable first-order model, the time constant is the resistance seen by the capacitor multiplied by its capacitance. A finite load changes that resistance. Use the entire connected network rather than multiplying capacitance by Rtop alone.

A reading taken before settling can look like ratio error, particularly when a scanner alternates between channels. Repeat the measurement at several delays without changing the hardware. A time-dependent approach to the predicted final value suggests a dynamic limitation. If the application changes voltage faster than the network can settle, a correct final DC ratio does not satisfy its actual measurement requirement; buffering or another impedance allocation may be necessary.

Balance loading against power and voltage stress

Reducing both divider resistances by the same factor preserves the unloaded ratio and reduces output resistance. It also increases current and power for the same applied voltage. The choice therefore requires a thermal assessment and a check of each element's voltage, not just a preferred input-impedance number. Neither the ceramic substrate nor a protective overglaze establishes an unrestricted power or voltage rating.

Increasing the receiver impedance may be a better solution, but a buffer brings its own bias current, offset, supply limits and stability requirements. Compare complete circuit options at the operating extremes. For a high-voltage divider, use appropriate rated equipment, protective arrangements and qualified personnel; a low-voltage loading experiment cannot establish insulation adequacy or permission to energize a high-voltage assembly.

Write a test that represents the installed circuit

Specify whether acceptance is based on isolated resistor values, an unloaded voltage ratio or a loaded transfer. If the product will drive a defined receiver, include its equivalent input conditions in the electrical test. Record source voltage at the divider terminals, receiver configuration, meter connections and the time between excitation and reading. These details make a discrepancy reproducible.

When several receivers are permitted, state a supported impedance range and evaluate the endpoints rather than silently calibrating for one convenient instrument. Retain raw input and output readings, not only their ratio, because source movement and grounding problems may otherwise disappear from the report. A useful RFQ can then distinguish a resistor manufacturing requirement from an interface correction that belongs in the surrounding electronics.

Define the divider and its receiver

Send the connected circuit so the unloaded ratio, loading error and operating stresses can be considered together.

  • Top and bottom resistor targets, circuit schematic and named voltage-reference terminals.
  • Input voltage range, source impedance and allowable output error.
  • Receiver resistance, leakage or bias current, capacitance and sampling timing where applicable.
  • Actual inspection instrument and all parallel connections used during measurement.
  • Mounting, power-state and temperature conditions for the finished circuit.

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