Resistor DAC Code Changes: Measure Glitch Area Separately from Settled Accuracy

System boundary

Printed resistor DAC network, switches, reference, output electronics and receiver. Dynamic switching error is evaluated separately from the settled code transfer.

Integration interfaces

Integration risks

Separate the passive weights from the switching event

An R–2R ladder and a binary-weighted resistor network establish different physical paths, even when both produce binary-weighted outputs. Their switches, reference source and output amplifier determine how the output moves between states. Specify the actual architecture and the output node observed. The same passive resistance values can participate in different dynamic behavior when the surrounding circuit changes.

Static acceptance measures the settled value at each code. Dynamic acceptance observes the interval between those settled states. Unequal switching delays and coupling can briefly create a combination of paths that is not the intended old or new code. Improving final resistor matching may improve static transfer without removing that transient. Treat switch timing, interconnect and receiver sensitivity as their own design inputs.

Define which waveform is called the error

Let the measured output be v(t) and the declared intended transition waveform be vref(t). Define transient error e(t) as v(t) minus vref(t), using volts and a common time origin. For a small adjacent-code change, vref might be the ideal step at the update event. For a different acceptance method it may use a documented transition reconstruction. State that choice before comparing results.

Subtracting only the final voltage across a record that includes the old state adds the commanded step itself to the calculated area. Subtracting a fitted smooth curve can remove part of the actual disturbance. Retain the raw waveform and both settled endpoint estimates so the baseline can be reconstructed. A numerical area without its baseline and integration interval is not a reproducible specification.

Keep voltage-time area distinct from physical energy

The signed glitch area is the integral of e(t) over the chosen interval. Its units are volt-seconds, commonly expressed as nanovolt-seconds. Despite the frequent name glitch energy, this quantity is not energy in joules. Actual energy delivered to a load requires the appropriate voltage-current or power integral, including the load model.

Also calculate positive area, negative area and the integral of the absolute error where they matter to the receiver. Signed positive and negative contributions can cancel numerically even though both excursions occurred. Preserve peak positive and negative voltages alongside the areas. An integrator, a threshold detector and a protection clamp can respond differently to exactly the same waveform.

Use a two-lobe example to expose cancellation

Assume a transient error consists of a positive triangular lobe with a 20 mV peak and 100 ns base width, followed by a negative triangular lobe with a 10 mV magnitude and 200 ns base width. A triangular area is half the peak times its base width. The two signed areas are therefore plus 1 nV·s and minus 1 nV·s.

The net area is zero, while the absolute area is 2 nV·s and the peak excursions remain plus 20 mV and minus 10 mV. A receiver limited to a 5 mV excursion would not pass this illustrative waveform merely because its signed area vanishes. These assumed shapes demonstrate the metric distinction; they are not a measured ChipSimple network response or a DAC performance rating.

Test more than one convenient major carry

For a binary code, an adjacent major carry turns a higher bit on while lower bits turn off. It is a useful stress transition, but it need not be the worst transient in a real converter. Test both directions and the code pairs relevant to the customer's normal operating sequence. Keep the update timing and reference or output load identical when comparing candidates.

Separate activity on the digital interface from an actual analog-code update when the hardware permits independent events. Clocking a command can couple to the output even if the output code does not change. Conversely, changing the analog register can introduce a conversion glitch after earlier digital activity has settled. Combining both into one capture is valid for a system test, but it should not be mislabeled as an isolated switch-only result.

Control bandwidth and the integration window

Capture enough bandwidth and time resolution to represent the fastest relevant excursion without clipping. Keep the acquisition settings with the result. A narrow-band measurement may reduce the observed peak while spreading the waveform in time; a window that then ends too early can also miss the delayed area. Repeat with expanded windows to confirm that the selected metric has converged adequately.

Check offset before integrating because even a small baseline error accumulates with time. For example, an uncorrected 0.2 mV offset over a 10 microsecond window contributes 2 nV·s, equal to the absolute area in the earlier example. Record pre-event and post-event baseline regions and avoid using a large arbitrary interval merely to make the displayed trace look complete.

Evaluate what the downstream circuit actually does

A linear low-pass stage can reduce a peak while extending the disturbance, so inspect both its transient and its settling into the required error band. A nonlinear receiver can rectify, clamp or trigger on an excursion; its response cannot be predicted from signed area alone. The appropriate criterion belongs to the application, not to whichever single number looks most favorable.

For repeated updates, retain the actual update interval and code history. A transient that has not settled before the next update can affect the apparent average output. Test the installed cadence and required receiver state rather than assuming that a clean isolated event proves continuous operation. A static endpoint calibration cannot generally correct a code- and timing-dependent disturbance.

Supply a dynamic acceptance record with the resistor network

For a ChipSimple DAC-network enquiry, provide the ladder topology, switch and reference circuits, output buffer and load. Identify which passive relationships require matching and which dynamic limits belong to the complete assembly. Keep the physical network terminals and interconnect layout tied to the tested revision so a change in connection geometry does not escape the transient review.

Deliver the raw captures, trigger reference, code pairs, baseline definition, integration intervals, peak limits and settling criterion. Include both the static transfer check and the dynamic receiver response without treating either as a substitute for the other. This lets the network and electronics owners resolve the actual failure mechanism instead of tightening an unrelated resistor tolerance after every observed glitch.