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A resistor network used in a binary digital-to-analog conversion path must do more than reach its two endpoints. When a higher bit turns on and several lower bits turn off, the resulting settled output should still move in the required direction. That major-carry transition exposes a relationship between several effective bit weights. Checking each resistance independently, or correcting overall gain and offset, does not directly verify that relationship.
For a drawing-specific part, review the Custom printed resistor network construction, product evidence and quotation inputs alongside this method. Prepare the resistance and tolerance tool with your operating conditions.
Key design decisions
- Define settled output, code polarity and the LSB convention before reporting monotonicity or differential nonlinearity.
- Evaluate each major carry using effective bit contributions, not just a list of individual resistor tolerances.
- Confirm that a fixed-weight linear model represents the actual switches, reference and load before using it to predict unmeasured codes.
Name the ladder topology and the complete conversion boundary
An R–2R ladder and a set of binary-weighted resistors are different physical constructions that can produce binary-weighted output contributions. The switch arrangement, reference connections and output loading determine the transfer. Current-steering and voltage-switching configurations must not share an assumed impedance model merely because both use resistors labeled R and 2R.
For a custom printed network, define the passive nodes separately from the switches and output electronics. The drawing review needs the actual topology and intended measurement boundary. Converter resolution is a property of the complete implemented transfer, not a capability established by the words matched resistors. Material route, ratio stability and interface effects must support the allocated transfer requirements.
Express each settled bit contribution in the same units
For an approximately linear fixed-state network, write output as an offset plus the sum of bit contributions. Let bi be zero or one and wi be the output increment produced by bit i, expressed in a common chosen LSB unit. The model is y(code) = y0 + sum(bi wi). An ideal eight-bit unipolar network has weights 1, 2, 4, 8, 16, 32, 64 and 128.
A practical characterization can estimate a weight by comparing a one-bit-on code with the all-zero code after settling. However, this is useful only if those weights remain valid when other bits change. Switch resistance that depends on state, reference movement with loading or output-amplifier nonlinearity can violate that assumption. Compare combined codes with the predicted sums before relying on a short basis measurement.
Calculate what changes at a major carry
At the transition from code 2^k − 1 to code 2^k, bit k turns on while all k lower bits turn off. Higher bits remain unchanged in the basic transition. The settled increment is therefore wk minus the sum of the lower weights. For ideal binary weights the increment is one LSB, because their lower-weight sum is 2^k − 1.
A positive increment preserves strict increase at that transition. A zero increment is nondecreasing but loses a distinct output step. A negative increment is a reversal. State which interpretation of monotonicity the requirement uses. Differential nonlinearity, with a nominated unit LSB, is the actual adjacent-code increment divided by that LSB minus one; it measures step size rather than total endpoint accuracy.
Δyk = wk − sum(wi, i = 0…k−1); DNLk = Δyk/LSB − 1
- wk is the effective contribution of the newly enabled bit.
- The sum includes the lower bits disabled by that carry.
- All weights and LSB use the same output-voltage, current or normalized unit convention.
Settled linear superposition with fixed bit weights and unchanged offset. Code-dependent switching, reference and loading errors require direct code measurements or a more complete circuit model.
Inspect a small mismatch at the largest carry
Assume the seven lower weights of an eight-bit model are ideal and the highest weight is 127.4 rather than 128 nominated LSB units. Code 127 then produces 127 units above offset, while code 128 produces 127.4. The increment is 0.4 LSB and its differential nonlinearity is minus 0.6 LSB. The highest effective bit weight is only 0.46875 percent below its ideal value, but that mismatch consumes 60 percent of this particular output step.
If the highest weight instead becomes 126.9 units, the same transition decreases output by 0.1 LSB. Correcting the overall gain using the endpoints cannot turn that negative increment positive: multiplication by a positive gain factor preserves its sign. Neither example assigns the effective weight error directly to one printed resistor; a circuit sensitivity calculation is needed to connect the two.
| Highest bit weight | Code 127 output | Code 128 output | Carry increment and consequence |
|---|---|---|---|
| 128 LSB | 127 LSB | 128 LSB | 1 LSB; nominated ideal step |
| 127.4 LSB | 127 LSB | 127.4 LSB | 0.4 LSB; compressed positive step |
| 126.9 LSB | 127 LSB | 126.9 LSB | −0.1 LSB; settled reversal |
Allocate bit-weight errors without relabeling resistor tolerance
For an illustrative twelve-bit model, the highest ideal weight is 2048 LSB and the sum of lower weights is 2047 LSB. If only the highest weight has error, preserving a carry increment of at least 0.5 LSB permits a negative fractional weight error no greater than 0.5/2048, approximately 244.1 parts per million.
If every effective weight can move adversely by the same fractional bound epsilon, the minimum major-carry increment is 1 − 4095 epsilon LSB. Preserving the same half-LSB increment then requires epsilon no greater than 0.5/4095, approximately 122.1 parts per million. This is a deliberately conservative bound on effective weights. It is not a twelve-bit resistor purchasing tolerance: real ladder sensitivities are coupled, and their correlations must be calculated or measured.
Keep common gain movement separate from local reversal
If all effective weights scale by the same positive factor, every adjacent-code increment scales with them. A common two-percent increase produces a 1.02 nominated-LSB ideal step throughout a perfectly weighted network. Under an endpoint-derived LSB convention, that common gain change is removed from differential nonlinearity, while it remains visible as gain error relative to the nominated reference scale.
Document which convention produced each result. Mixing nominated-LSB and endpoint-LSB calculations can make two valid reports look contradictory. Endpoint correction also does not remove unequal weight changes: a compressed major carry remains compressed relative to neighboring steps. Preserve raw endpoint values and raw adjacent-code differences so the normalization can be reproduced.
Separate the settled carry from its switching transient
A major carry changes several switches, so the transient can briefly follow a different path from the final settled increment. An output may overshoot during switching yet settle monotonically, or switch cleanly while settling to a lower final value. These are different acceptance questions and require different acquisition settings.
For static monotonicity, establish a sufficient settling interval and measurement uncertainty for both sides of each transition. Reverse the code sequence and repeat selected pairs to expose drift or hysteresis. For dynamic behavior, retain the time-domain waveform and actual update timing separately. Do not average away a static reversal by mixing pre-settled samples with final readings.
Use targeted carries to diagnose, then verify the required code range
Major-carry pairs are efficient diagnostic points, but they are not a substitute for all-code verification when the requirement covers every code. A complete eight-bit sweep contains 256 settled output values and 255 adjacent increments; a twelve-bit sweep contains 4096 values and 4095 increments. Retain the smallest increment and its code pair, not only an average linearity statistic.
If a passive network adjustment is proposed, predict its effect on all affected bit weights and preserve the physically allowed adjustment direction. Semiconductor trimming examples do not establish bidirectional laser adjustment of a fired resistor. After adjustment, remeasure the full affected transfer under the defined reference, load and temperature states. This connects the printed network's requirements to converter behavior without confusing bit count with demonstrated precision.
Provide the code-to-output requirement
Send the actual ladder and switching circuit so passive resistance relationships can be tied to settled output steps.
- Network schematic, switch connections, reference impedance, output electronics and permitted load states.
- Code width, polarity, nominated output span, LSB normalization and minimum permitted adjacent-code increment.
- Measured individual bit contributions and combined-code checks showing whether fixed-weight superposition is valid.
- Settled code sweep, major-carry pairs, measurement uncertainty, temperature and actual settling interval.
- Accessible trim regions, permitted resistance changes and separate static-linearity and dynamic-glitch requirements.
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