Insulation Surface Integration

Creepage Surfaces: Contamination and Assembly Changes after Manufacture

Recalculate exposed surface paths after assembly, cleaning residue and contamination are added to the manufactured ceramic circuit.

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High-resolution industrial engineering scene showing chemical exposure in a clean thick-film ceramic circuit context.
Engineering illustration; not a product photograph or a test result.
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A creepage path drawn on a bare ceramic image can be shortened, bridged or redirected after terminals, fasteners, adhesive, coating edges, labels and contamination are added. Cleaning can remove one residue while spreading another into a recessed interface. The process review walks the final assembly surface between named conductors, records material and pollution states, and returns the as-built geometry to the insulation-coordination owner. It does not publish a universal distance or safe voltage.

Key design decisions

  • Trace the final assembled surface path between exact nodes.
  • Identify every added material, edge and contamination trap.
  • Verify cleaning and coating without merging them with air clearance.

Walk the shortest final surface path in three dimensions

Start at one conductor boundary and follow the accessible insulating surface to the other, including ceramic edges, holes, coating boundaries and interfaces around attachments. Record air clearance separately. A raised bead may lengthen one route but create an interface that supports another. Fastener heads, metal housings and terminals can become intermediate conductive nodes. Use as-built dimensions and worst permitted assembly position. The responsible system engineer supplies voltage and insulation category.

Calculate residual path after geometric encroachments

Project each assembly feature onto the candidate surface route and recompute the shortest connected path. Do not add discontinuous segments that liquid or contamination cannot follow.

L_surface=min_paths Σ l_i; M_L=L_surface-L_required

  • l_i are contiguous portions of one physical insulating surface path.
  • L_surface is the shortest modeled assembled path.
  • L_required is supplied by the qualified insulation design.
  • M_L is geometric margin only, not a voltage rating.

Correct node identities, material interfaces and assembly positions; pollution and dielectric performance are reviewed separately.

Show how an assembly feature consumes geometric margin

For illustration, a bare-card surface route is 6.2 mm. A permitted terminal shift shortens it by 0.4 mm and an adhesive bead creates a 0.3 mm shortcut along its edge, leaving 5.5 mm. If the system owner supplies a 5.0 mm requirement for that exact condition, geometric margin is 0.5 mm before dimensional uncertainty. These numbers teach path accounting and are not a required distance or safe operating claim.

Map residues and traps created by the process sequence

Document paste, flux or joining residues, cleaning agent, rinse, drying, gloves, packaging and assembly materials. Inspect beneath terminal shoulders, along coating steps, around holes and at ceramic edges. A flat cleanliness coupon may not represent these traps. Select analytical methods with appropriate expertise and report detection boundaries. Visual cleanliness alone cannot establish surface conductivity. Keep specimen genealogy and do not clean an unexpected assembly before recording its electrical state.

Review tolerance states of terminals, fasteners and adhesives

Use minimum spacing positions, maximum bead spread, coating registration limits and worst relevant fastener location. Include rework and repair states if permitted. Compression can move an elastomer or adhesive after initial inspection. Thermal cycling can open or close gaps. Create cross-sections or dimensional studies on allocated specimens. Do not rely on nominal CAD overlap when dispensing and seating determine the actual boundary.

Changes to an assembled surface path
ChangeEvidenceInsulation-review input
Terminal placementAssembled positional limitsNew conductive boundary
Adhesive or coatingSpread, thickness and edgeChanged material interface
Cleaning residueProcess and analytical evidenceSurface-condition state
Housing or fastenerMinimum assembled locationAlternative path or node

Measure leakage as supporting evidence, not a distance substitute

Use guarded node-specific measurements at voltage, polarity, humidity, temperature and time authorized by the insulation owner. A passing leakage test on one clean unit does not replace dimensional control; a failing test does not reveal the path without localization. Record time dependence and fixture blanks. Coating capacitance and surface charging can affect transient current. High-voltage work requires qualified personnel and facility safety controls.

Avoid process fixes that create new surface interfaces

More coating can cover contamination, trap moisture or move a triple interface. More adhesive can reduce movement but flow toward conductive features. Aggressive cleaning can attack finishes or leave rinse residue. Evaluate any correction through material compatibility, geometry and electrical evidence. Preserve air clearance while modifying creepage surfaces. Confirm that protective coverage does not interfere with contacts, solder pads or heat transfer.

Return the final assembly path to the insulation owner

Provide card artwork, coating, terminals, fasteners, housing, adhesives, cleaning route, environmental state, tolerances and measured shortest paths. ChipSimple can control drawing-defined ceramic and thick-film features; system creepage, clearance, pollution and voltage compliance remain customer-owned. Reopen the review after changes to assembly, material, cleaning, coating, rework, enclosure, voltage or environment.

Preserve creepage on the surface that ships in the assembly

Creepage follows the finished insulating surface between conductive features; clearance follows the shortest path through the relevant medium. Both can change after the printed substrate leaves fabrication. Solder spread, clips, fasteners, adhesive squeeze-out, contamination and enclosure geometry may shorten the path or introduce a new conductive object. Build the review on a sectional assembly drawing rather than a bare-board distance alone. Identify which surfaces remain exposed, which are covered by qualified insulation and where users or grounded metal can approach.

Cleaning status must be defined at the point of acceptance. Residue from handling, soldering or assembly can change surface behavior even when geometric distance is unchanged. Protective glaze boundaries require clear coverage and edge rules, but glaze presence is not a substitute for system-level insulation coordination. The responsible design authority supplies working voltage, overvoltage category, pollution assumptions, altitude, material group and applicable standard. ChipSimple can review manufacturable geometry against those inputs without declaring universal compliance.

Verification combines dimensional measurement, visual coverage inspection and any specified electrical test. Gauge the actual conductive extremes, including solder meniscus or terminal hardware, and measure around obstacles along the defined surface route. Record conditioning and environment for leakage or withstand tests. RFQ inputs should include potential map, assembly cross-section, safety standard, coating or glaze construction, contamination controls and installation tolerances. A change to connector, solder amount, cleaning agent, enclosure, mounting hardware or field environment requires renewed creepage and clearance review.

For assemblies with several voltage domains, create a matrix of pairwise potential differences rather than checking only the highest system voltage. The shortest geometric pair may not carry the largest stress, and a grounded fastener can introduce a path absent from the circuit drawing. Mark accessible, grounded, floating and switched conductors. Evaluate polarity reversal and transient relationships if they are part of the customer requirement. This matrix becomes the inspection reference for final solder, hardware and coating placement, ensuring the finished assembly remains consistent with the insulation-coordination decision.

Provide the final assembled insulation-surface map

Creepage review needs every added material and conductor position after assembly.

  • Card artwork, conductor nodes, ceramic edges, holes and protective layers.
  • Terminals, housing, fasteners, adhesive, seals and positional tolerances.
  • Cleaning, contamination, humidity and other application states.
  • System-required paths, voltage conditions, safety and validation ownership.

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